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公开(公告)号：US20220197837A1
公开(公告)日：2022-06-23
申请号：US17407411
申请日：2021-08-20
Applicant: Micron Technology, Inc.
Inventor： Johnny A. Lam , Alex J. Wesenberg , Guanying Wu , Sanjay Subbarao , Chandra Guda
Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.
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公开(公告)号：US11868287B2
公开(公告)日：2024-01-09
申请号：US17407411
申请日：2021-08-20
Applicant: Micron Technology, Inc.
Inventor： Johnny A Lam , Alex J. Wesenberg , Guanying Wu , Sanjay Subbarao , Chandra Guda
CPC classification number: G06F13/1673 , G06F9/5016 , G06F13/161 , G06F13/37 , G06F2209/503 , G06F2209/5011
Abstract: The memory sub-systems of the present disclosure discloses a just-in-time (JIT) scheduling system and method. In one embodiment, a system receives a request to perform a memory operation using a hardware resource associated with a memory device. The system identifies a traffic class corresponding to the memory operation. The system determines a number of available quality of service (QoS) credits for the traffic class during a current scheduling time frame. The system determines a number of QoS credits associated with a type of the memory operation. Responsive to determining the number of QoS credits associated with the type of the memory operation is less than the number of available QoS credits, the system submits the memory operation to be processed at a memory device.
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3.发明公开
公开(公告)号：US20240176533A1
公开(公告)日：2024-05-30
申请号：US18433688
申请日：2024-02-06
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Winterfeld , Guanying Wu
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06F12/06
Abstract: Quad-to-single (Q2S) data structure comprising a plurality of entries maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list corresponding to a Q2S mapping entry associated with the QLC block stripe to be programmed.
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公开(公告)号：US20240078199A1
公开(公告)日：2024-03-07
申请号：US18506604
申请日：2023-11-10
Applicant: Micron Technology, Inc.
Inventor： Johnny A. Lam , Alex J. Wesenberg , Guanying Wu , Sanjay Subbarao , Chandra Guda
CPC classification number: G06F13/1673 , G06F9/5016 , G06F13/161 , G06F13/37 , G06F2209/5011 , G06F2209/503
Abstract: A just-in-time (JIT) scheduling method includes the operations of: receiving a request to perform a memory operation using a hardware resource associated with a memory device; determining a type of the memory operation; identifying a traffic class corresponding to the memory operation; determining, based on the traffic class and the type of the memory operation, whether the memory operation is to be processed during a current scheduling time frame; and responsive to determining the memory operation is to be processed during the current scheduling time frame, submitting the memory operation to the memory device.
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5.发明授权
公开(公告)号：US11934685B2
公开(公告)日：2024-03-19
申请号：US17578341
申请日：2022-01-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Winterfeld , Guanying Wu
CPC classification number: G06F3/0655 , G06F3/0604 , G06F3/0673 , G06F12/06
Abstract: A quad-to-single (Q2S) data structure comprising a plurality of the Q2S mapping entries is maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes of the non-volatile memory device with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list. The linked list corresponds to a Q2S mapping entry associated with the QLC block stripe to be programmed.
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6.发明公开
公开(公告)号：US20230229340A1
公开(公告)日：2023-07-20
申请号：US17578341
申请日：2022-01-18
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Michael Winterfeld , Guanying Wu
CPC classification number: G06F3/0655 , G06F12/06 , G06F3/0604 , G06F3/0673
Abstract: A quad-to-single (Q2S) data structure comprising a plurality of the Q2S mapping entries is maintained on a volatile memory device. Each Q2S mapping entry, identified by a physical address of a quad-level cell (QLC) block stripe of a non-volatile memory device, comprises a bit flag and a pointer to a linked list on the volatile memory device. Responsive to programming at least one single-level cell (SLC) block stripe of a plurality of SLC block stripes of the non-volatile memory device with data to be programmed to a QLC block stripe, an entry for an identification of the QLC block stripe to be programmed and an entry for each physical address of the at least one SLC block stripe of the plurality of SLC block stripes programmed with data to be programmed to the QLC block stripe is appended to a linked list. The linked list corresponds to a Q2S mapping entry associated with the QLC block stripe to be programmed.
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公开(公告)号：US20220197563A1
公开(公告)日：2022-06-23
申请号：US17407396
申请日：2021-08-20
Applicant: Micron Technology, Inc.
Inventor： Johnny A. Lam , Alex J. Wesenberg , Guanying Wu , Sanjay Subbarao , Chandra Guda
IPC: G06F3/06
Abstract: The memory sub-systems of the present disclosure discloses a simulator to simulate a QoS latency model for a just-in-time (JIT) scheduler. In one embodiment, a system receives a workload profile specifying a sequence of memory operations, wherein each memory operation is associated with a type of the memory operation. The system identifies a traffic class associated with each memory operation of the sequence of memory operations. The system queues each memory operation of the sequence of memory operations, based on the traffic class associated with the memory operation, in a scheduling pool of a number of scheduling pools. The system selects, based on a quality of service (QoS) policy, from the scheduling pools, one or more memory operations to be serviced within a scheduling time frame. The system determines, based on a latency profile, latency periods for each memory operation of the one or more memory operations.
