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    Monitoring flash memory erase progress using erase credits
    2.
    发明授权
    Monitoring flash memory erase progress using erase credits 有权

    公开(公告)号：US12182407B2

    公开(公告)日：2024-12-31

    申请号：US17346136

    申请日：2021-06-11

    Applicant: Micron Technology, Inc.

    Inventor： Giuseppe Cariello ,  Fulvio Rori ,  Jung Sheng Hoei

    IPC: G06F3/06

    Abstract: The progress of an erase operation for a memory device is monitored using an erase credit mechanism. In one approach, an erase operation is performed to erase a memory. Erase pulse slices used in the erase operation are monitored. Erase credits associated with the erase operation are determined. The erase credits include an erase credit associated with each of the erase pulse slices. Based on the erase credits, an extent of erasure of the memory is determined. In response to determining that the extent of erasure has reached a predetermined threshold, the erase operation is terminated.

    DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING
    5.
    发明公开
    DISTURB TRACKING AMONG MULTIPLE ERASE BLOCKS COUPLED TO A SAME STRING 审中-公开

    公开(公告)号：US20240168878A1

    公开(公告)日：2024-05-23

    申请号：US18386746

    申请日：2023-11-03

    Applicant: Micron Technology, Inc.

    Inventor： Akira Goda ,  Kishore K. Muchherla ,  Shyam Sunder Raghunathan ,  Leo Raimondo ,  Jung Sheng Hoei ,  Xiangang Luo ,  Ashutosh Malshe ,  Jianmin Huang

    IPC: G06F12/02

    CPC classification number: G06F12/0246

    Abstract: An apparatus can comprise a memory array comprising a plurality of strings of memory cells. Each string of the plurality of strings can comprise: a first group of memory cells coupled to a first group of access lines and corresponding to a first erase block; and a second group of memory cells coupled to a second group of access lines and corresponding to a second erase block. A controller is coupled to the memory array and configured to: perform a programming operation on the first group of memory cells of the first erase block; monitor a quantity of programming and/or erase operations performed on the second group of memory cells subsequent to the programming of the first group of memory cells; and perform an action on the first erase block responsive to the quantity of programming and/or erase operations performed on the second group of memory cells meeting a criteria.

    AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT
    8.
    发明申请
    AUTOMATIC WORDLINE STATUS BYPASS MANAGEMENT 有权

    公开(公告)号：US20230019189A1

    公开(公告)日：2023-01-19

    申请号：US17952927

    申请日：2022-09-26

    Applicant: Micron Technology, Inc.

    Inventor： Jiangang Wu ,  Jung Sheng Hoei ,  Qisong Lin ,  Kishore Kumar Muchherla

    IPC: G06F3/06

    Abstract: A processing device access a command to program data to a page in a block of a memory device. The processing device determines whether the page is a last remaining open page in the block. The processing device accesses a list that indicates enablement of a function to apply read level offsets to one or more open blocks in the memory device. The processing device determines the list includes an entry that matches to the block. The entry indicates enablement of the function to apply read level offsets to the block. The processing device disables the function based on determining the page is a last remaining open page in the block. The processing device adds the command to a prioritized queue of commands. The memory device executes commands from the prioritized queue in an order based on a priority level assigned to each command.

    NAND flash array defect real time detection
    10.
    发明授权
    NAND flash array defect real time detection 有权

    公开(公告)号：US11437117B2

    公开(公告)日：2022-09-06

    申请号：US16887516

    申请日：2020-05-29

    Applicant: Micron Technology, Inc.

    Inventor： Xiaojiang Guo ,  Jung Sheng Hoei ,  Michele Piccardi ,  Manan Tripathi

    IPC: G11C29/50 ,  G11C16/04 ,  G11C16/08 ,  G11C16/34 ,  G11C16/10

    Abstract: A memory device comprises a memory array; a word line driver circuit including a charge pump circuit configured to generate a program voltage target to be applied to a word line to program a memory cell of the memory array, and a control loop to activate the charge pump circuit using a control signal according to a comparison of a pump circuit output voltage to the program voltage target; a sensor circuit that compares a duty cycle of the control signal to a specified duty cycle after the charge pump circuit output reaches the program voltage target, and provides an indication of current generated by the charge pump circuit according to the duty cycle; and logic circuitry that generates a fault indication when the current generated by the charge pump circuit is greater than a specified threshold current.

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