公开(公告)号：US11568904B1

公开(公告)日：2023-01-31

申请号：US17451110

申请日：2021-10-15

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C7/10 ,  G11C7/12 ,  G11C5/14

Abstract: A memory is provided that includes a write multiplexer, which multiplexes among a plurality of bit line columns. The multiplexer includes a positive boost circuit that applies a positive boost to a voltage at the gates of transistors to strengthen an on state of those transistors. The positive boosting may be in addition to, or instead of, negative boosting at a write driver circuit.

公开(公告)号：US12094528B2

公开(公告)日：2024-09-17

申请号：US17833852

申请日：2022-06-06

Applicant: QUALCOMM Incorporated

Inventor： Dhvani Sheth ,  Hochul Lee ,  Anil Chowdary Kota ,  Chulmin Jung

IPC: G11C29/14 ,  G11C11/418 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/418

Abstract: A memory is provided with a plurality of column groups and two redundant column groups. If there are two defective columns in the plurality of column groups, the plurality of column groups may be divided into a no-shift region, a one-shift region, and a two-shift region. The memory includes a plurality of input/output circuits corresponding to the plurality of column groups. Each input/output circuit may provide a data input signal during a write operation and receive a data output signal during a read operation. Each input/output circuit also includes a switch matrix. In the no-shift region, the switch matrix couples the input/output circuit to a core in the corresponding column group. In the one-shift region, the switch matrix couples the input/output circuit to a core in a subsequent column group. In the two-shift region, the switch matrix couples the input/output circuit to a core in a next-to-subsequent column group.

公开(公告)号：US11250895B1

公开(公告)日：2022-02-15

申请号：US17089534

申请日：2020-11-04

Applicant: QUALCOMM Incorporated

Inventor： Dhvani Sheth ,  Anil Chowdary Kota ,  Hochul Lee ,  Chulmin Jung ,  Bin Liang

IPC: G11C8/00 ,  G11C8/08 ,  G11C8/10 ,  G11C16/30 ,  G11C7/10

Abstract: A memory device including: a first core of memory bitcells; a second core of memory bitcells; pre-decoding circuitry shared by the first core and the second core; and a row decoder coupled to the pre-decoding circuitry, the first core, and the second core, the row decoder including a first set-reset (SR) latch coupled to a first wordline of the first core and a second SR latch coupled to a second wordline of the second core.

公开(公告)号：US11894050B2

公开(公告)日：2024-02-06

申请号：US17481601

申请日：2021-09-22

Applicant: QUALCOMM Incorporated

Inventor： Hochul Lee ,  Anil Chowdary Kota ,  Dhvani Sheth ,  Chulmin Jung

IPC: G11C11/419 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes a self-timed memory circuit that controls the isolation of a sense amplifier from a column selected by a column multiplexer until the completion of a bit line voltage difference development delay. The self-timed memory circuit also controls the release of a pre-charge for the sense amplifier responsive to the completion of the bit line voltage difference development delay.

公开(公告)号：US12125526B2

公开(公告)日：2024-10-22

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Xiao Chen ,  Chi-Jui Chen ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.