公开(公告)号：US12125526B2

公开(公告)日：2024-10-22

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Xiao Chen ,  Chi-Jui Chen ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US11610633B2

公开(公告)日：2023-03-21

申请号：US17367248

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao Chen ,  Chen-ju Hsieh ,  Sung Son ,  Chulmin Jung

IPC: G11C16/00 ,  G11C16/10 ,  G11C16/26 ,  G11C17/12 ,  G11C16/08 ,  G11C16/04 ,  G11C16/24

Abstract: A drain programmed read-only memory includes a diffusion region that spans a width of a bitcell and forms a drain of a first transistor and a second transistor. A bit line lead in a metal layer adjacent the diffusion region extends across the width of the bitcell. A first via extends from an upper half of the bit line lead and couples to a drain of the first transistor. Similarly, a second via extends from a lower half of the bit line and couples to a drain of the second transistor.

公开(公告)号：US11450359B1

公开(公告)日：2022-09-20

申请号：US17366864

申请日：2021-07-02

Applicant: QUALCOMM Incorporated

Inventor： Xiao Chen ,  Po-Hung Chen ,  Chen-ju Hsieh ,  David Li ,  Chulmin Jung ,  Ayan Paul

IPC: G11C7/10 ,  G11C7/12 ,  H03K19/173 ,  G11C5/14 ,  H03K19/0185

Abstract: Various implementations provide systems and methods for writing data to memory bit cells. An example implementation includes a write circuit that couples both a bitline and a complementary bitline to power (VDD) by positive-channel metal oxide semiconductor (PMOS) transistors. By using PMOS transistors instead of NMOS transistors at the applicable nodes, such implementations may avoid a voltage drop between VDD and the bitlines, thereby allowing the bitlines to reach a substantially full VDD voltage level when appropriate. Additionally, various implementations avoid dynamic nodes that share charge across NMOS transistors, thereby allowing a given bitline to reach a substantially full VDD voltage level when appropriate. Accordingly, some implementations may experience higher levels of writability and static noise margin than other implementations.