公开(公告)号：US12125526B2

公开(公告)日：2024-10-22

申请号：US17657231

申请日：2022-03-30

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Xiao Chen ,  Chi-Jui Chen ,  Anil Chowdary Kota ,  Dhvani Sheth

IPC: G11C5/14 ,  G11C11/412 ,  G11C11/419

CPC classification number: G11C11/419 ,  G11C11/412

Abstract: A memory is provided that includes bitcell VDD boosting to increase a read margin. In some implementations, the positive boost for the bitcell VDD may be provided by a capacitor that is also used for negative boosting of a write driver.

公开(公告)号：US20210343330A1

公开(公告)日：2021-11-04

申请号：US16862238

申请日：2020-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Bin Liang ,  Chi-Jui Chen

IPC: G11C11/4094 ,  G11C11/4074 ,  G11C11/4096 ,  G11C7/12 ,  G11C5/02

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

公开(公告)号：US11488658B2

公开(公告)日：2022-11-01

申请号：US16862238

申请日：2020-04-29

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Bin Liang ,  Chi-Jui Chen

IPC: G11C11/4094 ,  G11C5/02 ,  G11C7/12 ,  G11C11/4074 ,  G11C11/4096

Abstract: Methods and apparatuses having an improved write assist scheme are presented. An apparatus includes a power supply node configured to provide power from a power supply to one memory cell to store data; a bitline configured to provide write data to the one memory cell in a write operation; and a discharge circuit configured to selectively discharge the power supply node to the bitline, based on the write data. A method to write into a memory cell with a write assist scheme includes providing power from a power supply to one memory cell via a power supply node, to store data; providing write data to the one memory cell via a bitline in a write operation; and discharging, selectively based on the write data, the power supply node to the bitline.

公开(公告)号：US11170865B1

公开(公告)日：2021-11-09

申请号：US16868402

申请日：2020-05-06

Applicant: QUALCOMM Incorporated

Inventor： Chulmin Jung ,  Bin Liang ,  Chi-Jui Chen

IPC: G11C29/00 ,  G11C29/02 ,  G11C29/20 ,  G11C29/12 ,  G11C29/44 ,  G11C29/10

Abstract: A method for a memory subsystem redundancy with priority decoding is described. The method includes dynamically repairing a local input/output (IO) unit of a first memory subsystem bank based on a current redundancy fuse input pattern of the first memory subsystem bank. The method also includes concurrently generating a redundancy shift signal in each global IO based on the current redundancy fuse input pattern to shift the repaired local IO unit and lower order local IO units of the first memory subsystem bank relative to the repaired local IO unit.