公开(公告)号：US20250056780A1

公开(公告)日：2025-02-13

申请号：US18723665

申请日：2022-01-06

Applicant: Siemens Industry Software Inc.

Inventor： Guy Shoshany

IPC: H05K13/08 ,  G06F30/398 ,  G06F111/20 ,  G06F115/12

Abstract: A method and a system for determining an assembling risk for an electronic component to be mounted to a printed circuit board. The method includes the following steps: providing a component library with a number of electronic components and its specific component identifier; wherein the component identifier includes an identifier string of letters and numbers providing information on a number of physical attributes of the electronic component; providing an evaluation scheme for each of the number of physical attributes; selecting an electronic component from the component library and evaluating each of the physical attributes; determining for each of the physical attributes the intermediate risk value and calculating from the intermediate risk values a final risk score; and determining the assembling risk associated with the final risk score by comparing the final risk score with a pre-defined risk scale.

公开(公告)号：US20250021538A1

公开(公告)日：2025-01-16

申请号：US18712096

申请日：2021-12-03

Applicant: Siemens Industry Software Inc.

Inventor： Andrew Fitt ,  Nusrat Hamid

IPC: G06F16/22 ,  G06F16/28

Abstract: A computer-implemented method of providing a view of a filtered hierarchical data structure is described. A user views an initial view of a hierarchical data structure showing at least one branch value at an nth level expansion and provides a filter. A pre-constructed query index corresponding to the filter is queried against the hierarchical data structure to identify unconfigured paths to descendant values of a first child of nth level branch value. The descendant value and branch values between the descendant value and the branch value shown in the nth level expansion are marked as displayable when the filter is met. The process is repeated for all other branch values shown in the initial view. A revised view showing only those values from the initial view in which the branch value, a child value, or a descendant value were marked as displayable is then displayed to the user.

公开(公告)号：US20240427967A1

公开(公告)日：2024-12-26

申请号：US18337907

申请日：2023-06-20

Applicant: Siemens Industry Software Inc.

Inventor： Yuansheng Ma ,  Le Hong ,  Junjiang Lei

IPC: G06F30/27 ,  G06F30/392

Abstract: Layout features in a layout design are classified into groups of layout features. A machine learning-based SRAF generation process is then performed to generate sub-resolution assist features for layout features in each of the groups of layout features. Each of the groups of layout features has a specific machine learning model. The machine learning-based SRAF generation process comprising: dividing regions where sub-resolution assist features are likely to be placed into areas of interest, extracting a feature vector for each of the areas of interest based on a layout area centered at the each of the areas of interest, determining whether the each of the areas of interest should be part of a sub-resolution assist feature by using the feature vector as an input of the specific machine learning model, and generating the sub-resolution assist features based on results of the determining.

公开(公告)号：US20240273849A1

公开(公告)日：2024-08-15

申请号：US18565272

申请日：2021-06-16

Applicant: Siemens Industry Software Inc.

Inventor： Roman Poya ,  Jean Cabello ,  Glen McCann

IPC: G06T19/20 ,  G06F30/12

CPC classification number: G06T19/20 ,  G06F30/12 ,  G06T2219/2021

Abstract: A computing system may include a linear mesh access engine configured to access a linear mesh and a target geometry as well as curved mesh generation engine configured to construct a curved mesh. Construction of the curved mesh may include projecting the linear mesh on to the target geometry to form a projected mesh, determining deformation patches included in the projected mesh, selecting a cost function to apply to the deformation patches from a set of available cost functions, iteratively adapting the deformation patches based on the selected cost function to obtain adjusted mesh elements, and forming the curved mesh as a combination of the adjusted mesh elements and portions of the projected mesh not determined as part of the deformation patches.

公开(公告)号：US20240232452A9

公开(公告)日：2024-07-11

申请号：US18278781

申请日：2021-02-26

Applicant: Siemens Industry Software Inc.

Inventor： Howard Mattson

IPC: G06F30/17

CPC classification number: G06F30/17

Abstract: A method of modifying instances of at least one part P including at least one entity e in a mechanical component design, is disclosed. A first part P1 has a local co-ordinate frame F and includes at least one entity ei. A transform T1 applied to the part P1 obtains a part instance P1T1 having an instance co-ordinate frame F1 in a common global space. At least one entity e1 in the part instance P1T1 is then marked as a positioning entity pe1 and grouped rigidly with the instance co-ordinate frame F1. Causing a positioning entity pe1 to move in the instance co-ordinate frame F1 causes all positioning entities pe1 in the instance co-ordinate frame F1 to move rigidly with the instance co-ordinate frame F1 and any unmarked entities e1 to move independently of the rigid grouping of positioning entities pe1.

公开(公告)号：US20240232402A9

公开(公告)日：2024-07-11

申请号：US18546623

申请日：2021-02-16

Applicant: Siemens Industry Software Inc.

Inventor： Max Clark ,  Alex Zigelboim ,  Keren Paryenti ,  Tal Zur

IPC: G06F21/62

CPC classification number: G06F21/6209

Abstract: A PCB analysis utilizes manufacturing capability data shared in a multi-tenant collaborative network in a mixed cloud and on-premise environment. Access to a tenant's account of a DFM application deployed on the tenant's premises is provided. The DFM application is enabled to activate the PCB analysis on a DFM profile with manufacturing capability data. The tenant's account requests a utilization authorization of a given DFM profile stored in a cloud data layer. When the utilization is authorized, the given DFM profile is downloaded embedded in a locked DFM envelope, which locks together the given DFM profile with an injected identifier of the authorized tenant's account. Via the DFM application, when logged into the tenant's account, the PCB analysis is activated by permitting the unlocking of the DFM profile from the DFM envelope only when the identifier of the tenant's account is the same as the injected identifier.

公开(公告)号：US12032892B2

公开(公告)日：2024-07-09

申请号：US17638315

申请日：2019-08-30

Applicant: Siemens Industry Software Inc.

Inventor： David A. Abercrombie ,  Mohamed Alimam Mohamed Selim ,  Mohamed Bahnas ,  Hazem Hegazy ,  Ahmed Hamed Fathi Hamed

IPC: G06F30/392 ,  G06F30/27 ,  G06F119/18

CPC classification number: G06F30/392 ,  G06F30/27 ,  G06F2119/18

Abstract: Systems and methods for analyzing a semiconductor layout design around a point of interest (POI) are disclosed. Semiconductor layout designs are a representation of an integrated circuit in terms of planar geometric shapes which make up the components of the integrated circuit, and are used to manufacture the integrated circuit. The layout design may be analyzed using one or more POI-based approaches to determine whether to modify the layout design. In one POI-based approach, set of kernels, tailored to the downstream application, are convolved with a representation of the layout design about or around the POI in order to generate a signature associated with the POI. In turn, the signatures may be analyzed based on the downstream application. Another POI-based approach consists of analyzing geometrical parameters associated with the POI, which may be used during a design stage to identify and modify problem areas in the layout design.

公开(公告)号：US20240219847A1

公开(公告)日：2024-07-04

申请号：US18558455

申请日：2021-08-30

Applicant: Siemens Industry Software Inc.

Inventor： Young Chang Kim ,  Marko P. Chew ,  Lianghong Yin ,  Abhinandan Nath ,  John L. Sturtevant

IPC: G03F7/00

CPC classification number: G03F7/706839 ,  G03F7/705 ,  G03F7/70633 ,  G03F7/7065

Abstract: This application discloses a hotspot identification system to generate process variability bands for structures of an integrated circuit capable of being fabricated utilizing at least one lithographic mask based, at least in part, on a mask layout data describing the lithographic mask and a distribution of manufacturing parameters during fabrication. The hotspot identification system can utilize the process variability bands to identify a subset of the structures that correspond to hotspots in the integrated circuit and identify corresponding values for the manufacturing parameters associated with the identified hotspots. A wafer testing system can implement a real-time wafer assessment process by comparing measured manufacturing parameters associated with a fabricated integrated circuit to the values for the manufacturing parameters associated with the identified hotspots, and dynamically identifying a disposition for the fabricated integrated circuit corresponding to one or more structures associated with the identified hotspot based on the comparison.

公开(公告)号：US20240193338A1

公开(公告)日：2024-06-13

申请号：US18064535

申请日：2022-12-12

Applicant: Siemens Industry Software Inc.

Inventor： Vladislav Liubich ,  Avneet Kaur ,  George P Lippincott

IPC: G06F30/392 ,  G03F7/20

CPC classification number: G06F30/392 ,  G03F7/70441

Abstract: Various aspects of the present disclosed technology relate to techniques for retargeting free-form layout features. In a retargeting process, anchor points are selected on boundary lines of layout features based on one or more predetermined conditions. Property values comprising spacing values and linewidth values for each of the anchor points are then determined. Based on the determined property values, positions of the anchor points are adjusted to derive new anchor points. Retargeted layout features are derived by using splines as interpolating curves passing through the new anchor points or as approximating curves passing near to but not necessarily through the new anchor points.

公开(公告)号：US12001771B2

公开(公告)日：2024-06-04

申请号：US17412404

申请日：2021-08-26

Applicant: Siemens Industry Software Inc.

Inventor： Peter Foelsche

IPC: G06F30/30 ,  G06F30/323 ,  G06F30/367

CPC classification number: G06F30/367 ,  G06F30/323

Abstract: A computing system implementing a design verification system can detect multiple analog design blocks in a circuit design describing an electronic device. The design verification system can generate equivalent networks for the analog design blocks using different sets of the parameters of the analog design blocks by selectively collapsing nodes and branches in the analog design blocks based on values of the different sets of the parameters. The equivalent networks can correspond to behavioral topologies of the analog design blocks having the different sets of the parameters. The design verification system can selectively compile a subset of the analog design blocks into multiple compiled variant models based on a comparison of the equivalent networks. The design verification system can include an analog simulator to simulate the analog design blocks in the circuit design using the compiled variant models.