公开(公告)号：US12131768B2

公开(公告)日：2024-10-29

申请号：US17896337

申请日：2022-08-26

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Yang Lu

IPC分类号： G11C11/406 ,  G11C11/4078 ,  G11C11/408

CPC分类号： G11C11/40618 ,  G11C11/40615 ,  G11C11/4078 ,  G11C11/4085

摘要： Systems and methods for multi-wordline direct refresh operations in response to a row hammer error in a memory bank. The approach includes detecting, by a row hammer mitigation component, a row hammer error in a memory bank; and then triggering, by the row hammer mitigation component, a response to the row hammer error. Further, a memory controller receives, from a mode register, data, based on an aliasing row counter policy, selecting a type of multi-wordline direct refresh operation to be performed on a plurality of victim memory rows within the memory bank, wherein the plurality of victim memory rows are dispersed across a plurality of memory sub-banks. The approach includes concurrently executing the selected multi-wordline direct refresh operation to the plurality of victim memory rows.

公开(公告)号：US12125517B2

公开(公告)日：2024-10-22

申请号：US17804414

申请日：2022-05-27

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Keun Soo Song

IPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

CPC分类号： G11C11/4074 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

摘要： This document describes apparatuses and techniques for multi-rail power transition. In various aspects, a power rail controller transitions a memory circuit (e.g., of a memory die) from a first power rail to a second power rail. The power rail controller then changes a voltage of the first power rail from a first voltage to a second voltage. The power rail controller may also adjust termination impedance or a clock frequency of the memory circuit before transitioning the memory circuit to the second power rail. The power rail controller then transitions the memory circuit from the second power rail to the first power rail to enable operation of the memory circuit at the second voltage. By so doing, the power rail controller may improve the reliability of memory operations when transitioning operation of the memory circuit from the first voltage to the second voltage.

公开(公告)号：US20240339152A1

公开(公告)日：2024-10-10

申请号：US18627960

申请日：2024-04-05

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Kang-Yong Kim ,  Wonjun Choi

IPC分类号： G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

CPC分类号： G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

摘要： Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

公开(公告)号：US20240321329A1

公开(公告)日：2024-09-26

申请号：US18680550

申请日：2024-05-31

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Kang-Yong Kim

IPC分类号： G11C7/10 ,  G11C29/46

CPC分类号： G11C7/1063 ,  G11C7/1066 ,  G11C7/1096 ,  G11C29/46

摘要： Methods, systems, and devices for selective access for grouped memory dies are described. A memory device may be configured with a select die access protocol for a group of memory dies that share a same channel. The protocol may be enabled by one or more commands from the host device, which may be communicated to each of the memory dies of the group via the channel. The command(s) may indicate a first set of one or more memory dies of the group for which a set of commands may be enabled and may also indicate a second set of one or more memory dies of the group for which at least a subset of the set of commands is disabled. When the select die access mode is enabled, the disabled memory dies may be restricted from performing the subset of commands received via the channel.

公开(公告)号：US20240192862A1

公开(公告)日：2024-06-13

申请号：US18582356

申请日：2024-02-20

申请人： Micron Technology, Inc.

发明人： Hyun Yoo Lee ,  Kang-Yong Kim

IPC分类号： G06F3/06

CPC分类号： G06F3/0619 ,  G06F3/0656 ,  G06F3/0679

摘要： Described apparatuses and methods provide automated error correction with memory refresh. Memory devices can include error correction code (ECC) technology to detect or correct one or more bit-errors in data. Dynamic random-access memory (DRAM), including low-power double data rate (LPPDR) synchronous DRAM (SDRAM), performs refresh operations to maintain data stored in a memory array. A refresh operation can be a self-refresh operation or an auto-refresh operation. Described implementations can combine ECC technology with refresh operations to determine a data error with data that is being refreshed or to correct erroneous data that is being refreshed. In an example, data for a read operation is checked for errors. If an error is detected, a corresponding address can be stored. Responsive to the corresponding address being refreshed, corrected data is stored at the corresponding address in conjunction with the refresh operation. Alternatively, data being refreshed can be checked for an error.

公开(公告)号：US20240177745A1

公开(公告)日：2024-05-30

申请号：US18520189

申请日：2023-11-27

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Yuan He ,  Kang-Yong Kim

IPC分类号： G11C7/08 ,  G11C7/10 ,  G11C29/52

CPC分类号： G11C7/08 ,  G11C7/1069 ,  G11C29/52

摘要： Apparatuses and techniques for implementing shareable usage-based disturbance circuitry are described. Shareable usage-based disturbance circuitry includes circuits (e.g., shared circuits) that manage usage-based disturbance across at least two sections of a bank of memory within a die of a memory device. In example implementations, the shareable usage-based disturbance circuitry includes a counter circuit and/or an error-correction-code circuit that is coupled to sense amplifiers associated with two neighboring sections. With the shareable usage-based disturbance circuitry, dies within the memory device can be cheaper to manufacture, can consume less power, and can have a smaller footprint with less complex signal routing compared to other dies with other circuits dedicated to mitigating usage-based disturbance within each section.

公开(公告)号：US11990199B2

公开(公告)日：2024-05-21

申请号：US17647152

申请日：2022-01-05

申请人： Micron Technology, Inc.

发明人： Taeksang Song ,  Saira Samar Malik ,  Hyunyoo Lee ,  Chinnakrishnan Ballapuram ,  Kang-Yong Kim

IPC分类号： G11C29/42 ,  G11C29/12 ,  G11C29/44

CPC分类号： G11C29/42 ,  G11C29/1201 ,  G11C29/4401

摘要： Methods, systems, and devices for centralized error correction circuit are described. An apparatus may include a non-volatile memory disposed on a first die and a volatile memory disposed on a second die (different than the first die). The apparatus may also include an interface controller disposed on a third die (different than the first die and the second die). The interface controller may be coupled with the non-volatile memory and the volatile memory and may include an error correction circuit that is configured to operate on one or more codewords received from the volatile memory.

公开(公告)号：US20240161796A1

公开(公告)日：2024-05-16

申请号：US18420404

申请日：2024-01-23

申请人： Micron Technology, Inc.

发明人： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC分类号： G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

CPC分类号： G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

摘要： Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20240079036A1

公开(公告)日：2024-03-07

申请号：US17930034

申请日：2022-09-06

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Mark Kalei Hadrick ,  Kang-Yong Kim

IPC分类号： G06F12/02 ,  G06F13/16

CPC分类号： G06F12/023 ,  G06F13/1668 ,  G06F2212/1016

摘要： Apparatuses and techniques for implementing a standalone mode are described. The standalone mode refers to a mode in which a die that is designed to operate as one of multiple dies that are interconnected can operate independently of another one of the multiple dies. Prior to connecting the die to the other die, the die can perform a standalone read operation and/or a standalone write operation in accordance with the standalone mode. In this way, testing (or debugging) can be performed during an earlier stage in the manufacturing process before integrating the die into an interconnected die architecture. For example, this type of testing can be performed at a wafer level or at a single-die-package (SDP) level. In general, the standalone mode can be executed independent of whether the die is connected to the other die.

公开(公告)号：US20240078041A1

公开(公告)日：2024-03-07

申请号：US17930044

申请日：2022-09-06

申请人： Micron Technology, Inc.

发明人： Yang Lu ,  Kang-Yong Kim

IPC分类号： G06F3/06

CPC分类号： G06F3/0659 ,  G06F3/0614 ,  G06F3/0673 ,  G06F12/0223

摘要： This document describes apparatuses and techniques for die-based rank management for a memory system. In various aspects, a die-based rank controller (controller) can determine which memory dies of a memory device are not functional to store data and correlate rank selections of a memory system to ranks of other memory dies (e.g., functional memory dies). The controller may store information that indicates the correlation or mapping of the rank selections to the ranks of the other memory dies to enable access to those ranks of the memory system. In some aspects, the controller receives a command to access the memory device with a rank selection, and the controller enables access to a corresponding rank based on the information. By so doing, aspects of die-based rank management enable memory packages with non-functional memory dies to be used instead of discarded, which can increase production utilization or lower manufacturing costs.