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    SELF-CALIBRATION IN A MEMORY DEVICE
    1.
    发明申请
    SELF-CALIBRATION IN A MEMORY DEVICE 有权

    公开(公告)号：US20240420789A1

    公开(公告)日：2024-12-19

    申请号：US18638379

    申请日：2024-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Jennifer E. Taylor ,  Eric J. Stave ,  Timothy M. Hollis ,  Chulkyu Lee ,  Chris Gregory Holub

    IPC: G11C29/12 ,  G11C29/20

    Abstract: Systems and methods include self-training an equalizer of a semiconductor device using the semiconductor device. The semiconductor device receives an indication of a condition for re-training of the equalizer. The semiconductor device operates the equalizer based on trained values derived during the self-training. The semiconductor device also determines that the condition has been met, and in response, the semiconductor device re-trains the equalizer without invocation of re-training by a host device coupled to the semiconductor device.

    APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING
    2.
    发明公开
    APPARATUS WITH SPEED SELECTION MECHANISM AND METHOD FOR OPERATING 审中-公开

    公开(公告)号：US20240305507A1

    公开(公告)日：2024-09-12

    申请号：US18584986

    申请日：2024-02-22

    Applicant: Micron Technology, Inc.

    Inventor： Chulkyu Lee ,  Timothy M. Hollis

    IPC: H04L25/03 ,  G06F13/16

    CPC classification number: H04L25/03267 ,  G06F13/1668 ,  H04L25/03057

    Abstract: Methods, apparatuses, and systems related to an apparatus for managing on-die inter-symbol interference (ISI) are described. The apparatus may include (1) a single communication path with a set of drivers and (2) an on-die ISI prevention circuit coupled to the communication path in parallel. The single communication path may be used to propagate a slower speed signal and a higher speed signal. The on-die ISI prevention circuit may be configured to adjust the propagated signal for one of the speeds to reduce the ISI in the communicated signal.

    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS
    3.
    发明公开
    APPARATUSES INCLUDING BALL GRID ARRAYS AND ASSOCIATED SYSTEMS 审中-公开

    公开(公告)号：US20240282691A1

    公开(公告)日：2024-08-22

    申请号：US18652515

    申请日：2024-05-01

    Applicant: Micron Technology, Inc.

    Inventor： David K. Ovard ,  Thomas Hein ,  Timothy M. Hollis ,  Walter L. Moden

    IPC: H01L23/498 ,  H01L23/00

    CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49822 ,  H01L24/16 ,  H01L2224/16227 ,  H01L2924/15311 ,  H01L2924/18161

    Abstract: Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.

    Programmable Memory Timing
    4.
    发明公开
    Programmable Memory Timing 审中-公开

    公开(公告)号：US20240161796A1

    公开(公告)日：2024-05-16

    申请号：US18420404

    申请日：2024-01-23

    Applicant: Micron Technology, Inc.

    Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

    IPC: G11C7/10 ,  G06F3/06 ,  G06F13/16 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/02 ,  G11C29/10

    CPC classification number: G11C7/1087 ,  G06F3/0679 ,  G06F13/1689 ,  G11C7/22 ,  G11C11/4093 ,  G11C29/022 ,  G11C29/028 ,  G11C29/10

    Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES
    7.
    发明公开
    APPARATUSES AND METHODS FOR COUPLING A PLURALITY OF SEMICONDUCTOR DEVICES 审中-公开

    公开(公告)号：US20240063188A1

    公开(公告)日：2024-02-22

    申请号：US18499087

    申请日：2023-10-31

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Matthew B. Leslie ,  Timothy M. Hollis ,  Roy E. Greeff

    IPC: H01L25/065 ,  H01L25/18

    CPC classification number: H01L25/0657 ,  H01L25/18 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06562

    Abstract: Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a point of coupling at an intermediate semiconductor device of the group, and the signal is propagated away from the point of coupling over different (e.g., opposite) signal paths to other semiconductor devices of the group. Loading from the point of coupling at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, having a point of coupling at semiconductor device at an end of the group (e.g., a lowest semiconductor device of a stack, a highest semiconductor device of the stack, etc.) and providing a signal therefrom. The more balanced topology may reduce a timing difference between when signals arrive at each of the semiconductor devices.

    Multiple concurrent modulation schemes in a memory system
    10.
    发明授权
    Multiple concurrent modulation schemes in a memory system 有权

    公开(公告)号：US11610613B2

    公开(公告)日：2023-03-21

    申请号：US17212708

    申请日：2021-03-25

    Applicant: Micron Technology, Inc.

    Inventor： Robert Nasry Hasbun ,  Timothy M. Hollis ,  Jeffrey P. Wright ,  Dean D. Gans

    IPC: G11C7/10 ,  G06F1/3234 ,  G06F13/42 ,  G11C11/22 ,  G11C11/4093

    Abstract: Methods, systems, and devices for multiple concurrent modulation schemes in a memory system are described. Techniques are provided herein to communicate data using a modulation scheme having at least three levels and using a modulation scheme having at least two levels within a common system or memory device. Such communication with multiple modulation schemes may be concurrent. The modulated data may be communicated to a memory die through distinct signal paths that may correspond to a particular modulation scheme. An example of a modulation scheme having at least three levels may be pulse amplitude modulation (PAM) and an example of a modulation scheme having at least two levels may be non-return-to-zero (NRZ).

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