Systems may include a central processing unit (CPU), a graphics processing unit (GPU), or a field programmable gate array (FPGA), or any combination thereof. At least one memory device may be connected to the CPU, the GPU, or the FPGA. The memory device(s) may include a device substrate including a microelectronic device and bond pads coupled with an active surface of the device substrate. A package substrate may be secured to the device substrate, the package substrate configured to route signals to and from the bond pads. A ball grid array may be supported on the package substrate. Each ball of the ball grid array positioned and configured to carry one of a high-bandwidth data signal or a high-frequency clock signal may be located only diagonally adjacent to any other balls of the ball grid array configured to carry another of a high-bandwidth data signal or a high-frequency clock signal.