-
公开(公告)号：US12119043B2
公开(公告)日：2024-10-15
申请号：US17898737
申请日：2022-08-30
发明人： Edmund Gieske , Sujeet Ayyapureddi , Yang Lu , Amitava Majumdar
IPC分类号： G11C11/4078 , G11C11/406
CPC分类号： G11C11/4078 , G11C11/40615 , G11C11/40618
摘要： Practical, energy-efficient, and area-efficient, mitigation of errors in a memory media device that are caused by row hammer attacks and the like is described. The detection of errors is deterministically performed while maintaining, in an SRAM, a number of row access counters that is smaller than the total number of rows protected in the memory media device. The mitigation may be implemented on a per-bank basis. The memory media device may be DRAM.
-
2.发明公开公开(公告)号：US20240338126A1
公开(公告)日：2024-10-10
申请号：US18627859
申请日：2024-04-05
发明人： Kang-Yong Kim , Yang Lu , Wonjun Choi , Mark Kalei Hadrick
IPC分类号： G06F3/06
CPC分类号： G06F3/0619 , G06F3/0653 , G06F3/0673
摘要： Apparatuses and techniques for implementing collision avoidance for bank-shared circuitry that supports usage-based disturbance mitigation are described. A memory device includes bank-shared circuitry coupled to multiple banks. The bank-shared circuitry can support usage-based disturbance mitigation. By using the bank-shared circuitry to service multiple banks, the memory device can have a smaller footprint and can be cheaper to manufacture compared to other memory devices with circuitry dedicated for each bank. To avoid conflicts associated with some sequences of commands that may relate to a same bank or different banks and utilize the bank-shared circuitry, the memory controller applies an appropriate timing offset (or delay) between commands. The timing offset allows the memory device time to finish utilizing the bank-shared circuitry for usage-based disturbance mitigation prior to utilizing the bank-shared circuitry in accordance with a subsequent command.
-
公开(公告)号：US12086270B2
公开(公告)日：2024-09-10
申请号：US18166365
申请日：2023-02-08
发明人： Yang Lu , Markus H. Geiger , Nathaniel J. Meier
CPC分类号： G06F21/577 , G06F21/554 , G11C8/18 , G11C29/022 , G11C29/50004 , G11C29/52 , G06F2221/034 , G11C2029/5002
摘要： There are provided systems and methods that include at least one memory that has a plurality of memory cells. The cells may be disposed in rows and columns. The device can further include a controller that is communicatively coupled to the at least one memory, and the controller may be configured by its hardware topology and its instruction set and/or by a communicatively coupled processor or higher-level system or subsystem to maintain data integrity in the at least one memory and/or to prevent or mitigate malicious access patterns that may compromise the at least one memory. The controller may be configured to execute a deterministic protocol in conjunction with or sequentially to a probabilistic protocol to achieve one or more of the above-noted functions.
-
公开(公告)号：US12074615B2
公开(公告)日：2024-08-27
申请号：US17969856
申请日：2022-10-20
发明人： Marco Sforzin , Paolo Amato , Yang Lu
CPC分类号： H03M13/152 , G06F13/4221 , H03M13/095
摘要： Methods, systems, and devices related to mapping a plurality of pairs of bits of a memory transfer block (MTB) to a plurality of linked (LK) die input/output (LDIO) lines coupling a LK die to an interface (IF) die. The plurality of pairs of bits of the MTB can be communicated from the LK die to the IF die via the plurality of LDIO lines. Responsive to a failure of one of the plurality of LDIO lines, a Bose-Chaudhuri-Hocquenghem (BCH) error correction can be performed on the pairs of bits mapped to the failed LDIO line. Each of the plurality of pairs of bits is a respective symbol for the BCH error correction.
-
公开(公告)号：US20240202145A1
公开(公告)日：2024-06-20
申请号：US18540427
申请日：2023-12-14
发明人： Yang Lu , Kang-Yong Kim
CPC分类号： G06F13/1684 , G06F13/1689 , G06F13/4234
摘要： This disclosure describes aspects of memory die interconnections to physical layer interfaces (PHYs) that may enable expanded channel bus width and improved signal integrity (SI). In aspects, a memory die is operably coupled to a first PHY via a command-and-address (CA) bus and data input/output (DQ) bus of the first PHY and to a second PHY via a chip select (CS) bus of the second PHY. The second PHY may provide a CS signal to the memory die, and the first PHY can perform a training procedure via CA signaling or DQ signaling. The training procedure may improve SI between the memory die and the PHYs. Additionally, a memory die may be interconnected to different PHYs to expand a channel bus width. Thus, by interconnecting memory dies to one or more PHYs as described herein, improved SI and expanded channel bus width can be achieved.
-
公开(公告)号：US20230052489A1
公开(公告)日：2023-02-16
申请号：US17818413
申请日：2022-08-09
发明人： Hyunyoo Lee , Kang-Yong Kim , Yang Lu
IPC分类号： G11C7/10 , H03K19/173 , H03K19/017
摘要： Methods, systems, and devices for die location detection for grouped memory dies are described. A memory device may include multiple memory die that are coupled with a shared bus. In some examples, each memory die may include a circuit configured to output an identifier associated with a location of the respective memory die. For example, a first memory die may output a first identifier, based on receiving one or more signals, that identifies a location of the first memory die. Identifying the locations of the respective memory dies may allow for the dies to be individually accessed despite being coupled with a shared bus.
-
公开(公告)号：US20220366994A1
公开(公告)日：2022-11-17
申请号：US17317006
申请日：2021-05-11
发明人： Zhenming Zhou , Yang Lu , Jiangli Zhu , Tingjun Xie
摘要： A system and method for measuring the degradation of one or more memory devices of a memory sub-system. An example system including a memory controller operatively coupled with a memory device and configured to perform operations comprising: testing different values for a setting of the memory device, wherein the setting of the memory device affects a duty cycle of a signal internal to the memory device; selecting an optimum value for the setting based on access errors during the testing, wherein the optimum value minimizes access errors; determining a degradation measurement for the memory device based on the optimum value; and providing a notification to a host system based on the degradation measurement.
-
公开(公告)号：US11340831B2
公开(公告)日：2022-05-24
申请号：US17006580
申请日：2020-08-28
摘要： A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a read training setting configured to adjust a read output timing of data being sent to the memory controller during read operations from the one or more memory devices.
-
公开(公告)号：US20220066694A1
公开(公告)日：2022-03-03
申请号：US17006580
申请日：2020-08-28
摘要： A memory system is provided. The memory system includes a memory controller and a data bus electrically coupled to the memory controller. The memory system further includes one or more memory devices communicatively coupled to the memory controller via the data bus, wherein each of the one or more memory devices comprises a read training setting configured to adjust a read output timing of data being sent to the memory controller during read operations from the one or more memory devices.
-
公开(公告)号：US11017878B1
公开(公告)日：2021-05-25
申请号：US16719911
申请日：2019-12-18
摘要： Methods, systems, and devices for memory device with a dynamic fuse array are described. Techniques and apparatus are described herein for storing an address of a set of the array of latches that is associated with a set of the array of fuses. A se of an array of fuses may include a first portion for indicating the value of the parameter and a second portion for indicating an address of a set of the array of latches that is to receive the parameter stored in the first portion. An enabled set of fuses may indicate that the block is storing a value of a parameter for operating the memory device. By storing the address for the set of the array latches in the set of the array of fuses, a memory device may have a dynamic mapping between the array of latches and the array of fuses. Such a dynamic mapping may reduce an area used by the array of fuses and may make some parameters modifiable.
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.01 秒)
