公开(公告)号：US20180095888A1

公开(公告)日：2018-04-05

申请号：US15820462

申请日：2017-11-22

申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION

发明人： Kevin J. Ash ,  Lokesh M. Gupta

IPC分类号： G06F12/0891

CPC分类号： G06F12/0891 ,  G06F11/1076 ,  G06F12/0804 ,  G06F12/0868 ,  G06F2212/22 ,  G06F2212/224 ,  G06F2212/262

摘要： Provided are a computer program product, system, and method for considering a density of tracks to destage in groups of tracks to select groups of tracks to destage. Groups of tracks in the cache are scanned to determine whether they are ready to destage. A determination is made as to whether the tracks in one of the groups are ready to destage in response to scanning the tracks in the group. A density for the group is increased in response to determining that the group is not ready to destage. The group is destaged in response to determining that the density of the group exceeds a density threshold.

公开(公告)号：US20170286210A1

公开(公告)日：2017-10-05

申请号：US15087797

申请日：2016-03-31

申请人： INTEL CORPORATION

发明人： Theodros YIGZAW ,  Ashok RAJ ,  Robert SWANSON ,  Mohan J. KUMAR

IPC分类号： G06F11/07 ,  G06F12/08

CPC分类号： G06F11/0793 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/1064 ,  G06F12/0804 ,  G06F12/0811 ,  G06F2212/1021 ,  G06F2212/1032 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7201

摘要： An apparatus is described that includes memory controller logic circuitry to interface with a memory side cache of a multi-level system memory. The memory controller logic circuitry includes error tracking circuitry to track errors of cache line slots in the memory side cache. The memory controller logic circuitry also comprises faulty list circuitry to store identifiers of faulty cache line slots that are deemed to be excessively error prone. The memory controller logic circuitry is to declare a miss in the memory side cache for requests that map to cache line slots identified in the faulty list.

公开(公告)号：US20160378396A1

公开(公告)日：2016-12-29

申请号：US14752554

申请日：2015-06-26

申请人： Intel Corporation

发明人： Raj K. Ramanujan ,  Jun Zhu ,  Mohamed Arafa ,  Woojong Han ,  Jordan A. Horwich

IPC分类号： G06F3/06 ,  G06F12/10 ,  G06F12/08

CPC分类号： G06F3/0649 ,  G06F3/0616 ,  G06F3/0685 ,  G06F12/0246 ,  G06F12/0866 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/7211

摘要： Embodiments are generally directed to accelerated address indirection table lookup for wear-leveled non-volatile memory. A embodiment of a memory device includes nonvolatile memory; a memory controller; and address indirection logic to provide address indirection for the nonvolatile memory, of the address indirection logic to maintain an address indirection table (AIT) in the nonvolatile memory, the AIT including a plurality of levels, and copy at least a portion of the AIT to a second memory, the second memory having less latency than the first memory.

摘要翻译： 实施例通常涉及用于磨损级别的非易失性存储器的加速地址间接表查找。 存储器件的实施例包括非易失性存储器; 内存控制器 以及地址间接逻辑以提供所述非易失性存储器的地址间接，所述地址间接逻辑用于在所述非易失性存储器中维护地址间接表（AIT），所述AIT包括多个级别，并将所述AIT的至少一部分复制到 第二存储器，第二存储器具有比第一存储器更少的延迟。

公开(公告)号：US20160147480A1

公开(公告)日：2016-05-26

申请号：US15013343

申请日：2016-02-02

申请人： Seagate Technology LLC

发明人： Luke W. Friendshuh ,  Brian T. Edgar ,  Mark A. Gaertner

IPC分类号： G06F3/06 ,  G06F12/08

CPC分类号： G06F3/0647 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0866 ,  G06F12/0868 ,  G06F2212/21 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/224 ,  G06F2212/225 ,  G06F2212/28 ,  G06F2212/31 ,  G06F2212/46

摘要： The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

摘要翻译： 本公开涉及管理存储器件中的数据存储的系统和方法。 在一个具体实施例中，公开了一种方法，其包括在数据存储设备中接收至少一个数据分组，所述数据分组的大小与所分配的数据存储介质上的至少一个物理目的地位置的分配的存储容量不同 用于所述至少一个数据分组的数据存储设备。 该方法还包括在将至少一个接收到的数据分组传送到至少一个物理目的地位置之前，将至少一个接收到的数据分组存储在非易失性高速缓冲存储器中。

公开(公告)号：US20160092355A1

公开(公告)日：2016-03-31

申请号：US14963201

申请日：2015-12-08

申请人： QUALCOMM INCORPORATED

发明人： Xiangyu DONG ,  Xiaochun ZHU ,  Jungwon SUH

IPC分类号： G06F12/08

CPC分类号： G06F12/0802 ,  G06F12/08 ,  G06F12/0855 ,  G06F12/0864 ,  G06F2212/1016 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/60 ,  G11C7/1015 ,  G11C7/1039 ,  G11C7/1084 ,  G11C11/165 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0002 ,  G11C2207/2245 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229

摘要： A method of reading from and writing to a resistive memory cache includes receiving a write command and dividing the write command into multiple write sub-commands. The method also includes receiving a read command and executing the read command before executing a next write sub-command.

公开(公告)号：US20120151134A1

公开(公告)日：2012-06-14

申请号：US13292169

申请日：2011-11-09

申请人： Luke W. Friendshuh ,  Brian T. Edgar ,  Mark A. Gaertner

发明人： Luke W. Friendshuh ,  Brian T. Edgar ,  Mark A. Gaertner

IPC分类号： G06F12/08

CPC分类号： G06F3/0647 ,  G06F3/0604 ,  G06F3/0635 ,  G06F3/0685 ,  G06F12/0802 ,  G06F12/0866 ,  G06F12/0868 ,  G06F2212/21 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/224 ,  G06F2212/225 ,  G06F2212/28 ,  G06F2212/31 ,  G06F2212/46

摘要： The disclosure is related to systems and methods of managing data storage in a memory device. In a particular embodiment, a method is disclosed that includes receiving, in a data storage device, at least one data packet that has a size that is different from an allocated storage capacity of at least one physical destination location on a data storage medium in the data storage device for the at least one data packet. The method also includes storing the at least one received data packet in a non-volatile cache memory prior to transferring the at least one received data packet to the at least one physical destination location.

摘要翻译： 本公开涉及管理存储器件中的数据存储的系统和方法。 在一个具体实施例中，公开了一种方法，其包括在数据存储设备中接收至少一个数据分组，所述数据分组的大小与所分配的数据存储介质上的至少一个物理目的地位置的分配的存储容量不同 用于所述至少一个数据分组的数据存储设备。 该方法还包括在将至少一个接收到的数据分组传送到至少一个物理目的地位置之前，将至少一个接收到的数据分组存储在非易失性高速缓冲存储器中。

公开(公告)号：US20090222617A1

公开(公告)日：2009-09-03

申请号：US12394875

申请日：2009-02-27

申请人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

发明人： Junji YANO ,  Hidenori Matsuzaki ,  Kosuke Hatsuda

IPC分类号： G06F12/00 ,  G06F12/12 ,  G06F12/02

CPC分类号： G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C29/88 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.

摘要翻译： 存储器系统包括：易失性第一存储单元，以预定单元管理数据的非易失性第二存储单元;以及控制器，其经由第一存储单元将主机设备请求的数据写入第二存储单元，并读出数据 由主机从第二存储单元请求到第一存储单元，并将数据传送到主机设备。 控制器包括管理表，用于管理出现在第二存储单元中的预定单元中的故障区域的数量，并且根据故障区域的数量，切换从主机设备向第二存储单元写入数据的操作模式 。

公开(公告)号：US12130884B2

公开(公告)日：2024-10-29

申请号：US17374988

申请日：2021-07-13

申请人： Samsung Electronics Co., Ltd.

发明人： Peng Gu ,  Krishna Malladi ,  Hongzhong Zheng ,  Dimin Niu

IPC分类号： G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06N3/08

CPC分类号： G06F17/16 ,  G06F12/0802 ,  G06F12/0877 ,  G06N3/008 ,  G06N3/045 ,  G06N3/063 ,  G06F2212/1024 ,  G06F2212/1036 ,  G06F2212/22 ,  G06N3/08

摘要： A general matrix-matrix multiplication (GEMM) dataflow accelerator circuit is disclosed that includes a smart 3D stacking DRAM architecture. The accelerator circuit includes a memory bank, a peripheral lookup table stored in the memory bank, and a first vector buffer to store a first vector that is used as a row address into the lookup table. The circuit includes a second vector buffer to store a second vector that is used as a column address into the lookup table, and lookup table buffers to receive and store lookup table entries from the lookup table. The circuit further includes adders to sum the first product and a second product, and an output buffer to store the sum. The lookup table buffers determine a product of the first vector and the second vector without performing a multiply operation. The embodiments include a hierarchical lookup architecture to reduce latency. Accumulation results are propagated in a systolic manner.

公开(公告)号：US11822474B2

公开(公告)日：2023-11-21

申请号：US17830257

申请日：2022-06-01

申请人： FLC Global, Ltd.

发明人： Sehat Sutardja

IPC分类号： G06F12/0811 ,  G06F12/0864 ,  G11C11/406 ,  G06F12/0804 ,  G06F12/0868 ,  G06F12/0897 ,  G06F3/06 ,  G06F12/10 ,  G06F12/1027 ,  G06F9/4401 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/06

CPC分类号： G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G11C11/40607 ,  G06F12/0607 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/608 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/62 ,  Y02D10/00

摘要： A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20190196723A1

公开(公告)日：2019-06-27

申请号：US16293144

申请日：2019-03-05

申请人： Toshiba Memory Corporation

发明人： Junji YANO ,  Hidenori MATSUZAKI ,  Kosuke HATSUDA

IPC分类号： G06F3/06 ,  G06F12/0804 ,  G06F12/0866 ,  G11C29/00 ,  G06F11/07 ,  G06F12/0802 ,  G06F12/02

CPC分类号： G06F3/0614 ,  G06F3/0631 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0685 ,  G06F11/073 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0804 ,  G06F12/0866 ,  G06F2212/1032 ,  G06F2212/2022 ,  G06F2212/22 ,  G06F2212/7202 ,  G11C29/88 ,  G11C2029/0409 ,  G11C2029/0411

摘要： A memory system includes a volatile first storing unit, a nonvolatile second storing unit in which data is managed in a predetermined unit, and a controller that writes data requested by a host apparatus in the second storing unit via the first storing unit and reads out data requested by the host apparatus from the second storing unit to the first storing unit and transfers the data to the host apparatus. The controller includes a management table for managing the number of failure areas in a predetermined unit that occur in the second storing unit and switches, according to the number of failure areas, an operation mode in writing data in the second storing unit from the host apparatus.