公开(公告)号：US09928172B2

公开(公告)日：2018-03-27

申请号：US15454306

申请日：2017-03-09

Applicant: Marvell World Trade Ltd.

Inventor： Sehat Sutardja

IPC: G06F12/00 ,  G06F12/0811 ,  G06F12/0862 ,  G06F12/0813 ,  G06F12/1027 ,  G06F12/0864

CPC classification number: G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G06F2003/0691 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/608 ,  G06F2212/62 ,  G11C11/40607 ,  Y02D10/13

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US20170177481A1

公开(公告)日：2017-06-22

申请号：US15454306

申请日：2017-03-09

Applicant: Marvell World Trade Ltd.

Inventor： Sehat Sutardja

IPC: G06F12/0811 ,  G06F12/0813 ,  G06F12/1027 ,  G06F12/0862

CPC classification number: G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G06F2003/0691 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/608 ,  G06F2212/62 ,  G11C11/40607 ,  Y02D10/13

Abstract: A data access system including a processor and a storage system including a main memory and a cache module. The cache module includes a FLC controller and a cache. The cache is configured as a FLC to be accessed prior to accessing the main memory. The processor is coupled to levels of cache separate from the FLC. The processor generates, in response to data required by the processor not being in the levels of cache, a physical address corresponding to a physical location in the storage system. The FLC controller generates a virtual address based on the physical address. The virtual address corresponds to a physical location within the FLC or the main memory. The cache module causes, in response to the virtual address not corresponding to the physical location within the FLC, the data required by the processor to be retrieved from the main memory.

公开(公告)号：US09594693B2

公开(公告)日：2017-03-14

申请号：US15137611

申请日：2016-04-25

Applicant: Marvell World Trade Ltd.

Inventor： Sehat Sutardja

IPC: G06F12/00 ,  G06F12/10 ,  G06F12/08 ,  G11C11/406 ,  G06F3/06 ,  G06F9/44

CPC classification number: G06F12/0811 ,  G06F3/061 ,  G06F3/0613 ,  G06F3/0638 ,  G06F3/0655 ,  G06F3/0656 ,  G06F3/0679 ,  G06F3/0683 ,  G06F9/4406 ,  G06F12/0804 ,  G06F12/0813 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0868 ,  G06F12/0897 ,  G06F12/10 ,  G06F12/1027 ,  G06F2003/0691 ,  G06F2212/1016 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/171 ,  G06F2212/20 ,  G06F2212/202 ,  G06F2212/214 ,  G06F2212/22 ,  G06F2212/222 ,  G06F2212/251 ,  G06F2212/305 ,  G06F2212/50 ,  G06F2212/60 ,  G06F2212/6022 ,  G06F2212/6032 ,  G06F2212/608 ,  G06F2212/62 ,  G11C11/40607 ,  Y02D10/13

Abstract: A data access system including a storage drive, processor and cache module. The processor, in response to data required by the processor not being cached within one or more levels of cache of the processor, generates a first physical address (PA). The cache module includes a memory and first and second controllers. The memory is a final level of cache. The first controller converts the first PA into a virtual address. The second controller: converts the virtual address into a second PA; based on the second PA, determines whether the data is cached within the memory; and if the data is cached, accesses and forwards the data to the processor. The first or second controller determines whether a cache miss has occurred and, in response to a cache miss and based on the second PA or a third PA of the storage drive, retrieves the data from the storage drive.

Abstract translation: 包括存储驱动器，处理器和缓存模块的数据访问系统。 处理器响应于处理器未被缓存在处理器的高速缓存的一个或多个级别中所需的数据，生成第一物理地址（PA）。 高速缓存模块包括存储器和第一和第二控制器。 内存是最后一级缓存。 第一个控制器将第一个PA转换为虚拟地址。 第二个控制器：将虚拟地址转换成第二个PA; 基于第二PA，确定数据是否被缓存在存储器内; 并且如果数据被缓存，则访问并将数据转发到处理器。 第一或第二控制器确定高速缓存未命中是否已经发生，并且响应于高速缓存未命中并且基于第二PA或存储驱动器的第三PA，从存储驱动器检索数据。

公开(公告)号：US20160320972A1

公开(公告)日：2016-11-03

申请号：US14699714

申请日：2015-04-29

Applicant: QUALCOMM INCORPORATED

Inventor： Gurvinder Singh Chhabra ,  Andres Alejandro Oportus Valenzuela

IPC: G06F3/06

CPC classification number: G06F3/064 ,  G06F1/324 ,  G06F1/3275 ,  G06F1/3296 ,  G06F3/0608 ,  G06F3/0673 ,  G06F12/08 ,  G06F2212/1024 ,  G06F2212/1028 ,  G06F2212/161 ,  G06F2212/401 ,  H03M7/30 ,  H03M7/702 ,  Y02D10/126 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems, methods, and computer programs are disclosed for adaptive compression-based demand paging. Two or more compressed software image segments are stored in each of one or more memories. Each compressed software image segment corresponds to at least one software task and includes one or more pages that are compressed in accordance with a compression characteristic different from that of the other software image segments. If it is determined that a page request associated with an executing software task identifies a page that is not stored in the system memory, then a portion of the compressed software image segment containing the identified page is decompressed, and the decompressed page is stored in the system memory.

Abstract translation: 公开了用于基于自适应压缩的需求寻呼的系统，方法和计算机程序。 两个或多个压缩软件图像段存储在一个或多个存储器的每一个中。 每个压缩软件图像段对应于至少一个软件任务，并且包括根据与其他软件图像段的压缩特性不同的压缩特性压缩的一个或多个页面。 如果确定与执行软件任务相关联的寻呼请求识别未存储在系统存储器中的页面，则解压缩包含所识别页面的压缩软件图像段的一部分，并将解压缩页存储在 系统内存

公开(公告)号：US20160085680A1

公开(公告)日：2016-03-24

申请号：US14958655

申请日：2015-12-03

Applicant: Memory Technologies LLC

Inventor： Matti Floman ,  Kimmo J. Mylly

IPC: G06F12/08

CPC classification number: G06F12/0862 ,  G06F2212/1024 ,  G06F2212/161 ,  G06F2212/6026 ,  Y02D10/13

Abstract: Examples of enabling cache read optimization for mobile memory devices are described. One or more access commands may be received, from a host, at a memory device. The one or more access commands may instruct the memory device to access at least two data blocks. The memory device may generate pre-fetch information for the at least two data blocks based at least in part on an order of accessing the at least two data blocks.

Abstract translation: 描述了为移动存储设备启用高速缓存读取优化的示例。 可以从主机在存储设备处接收一个或多个访问命令。 一个或多个访问命令可以指示存储器设备访问至少两个数据块。 至少部分地基于访问至少两个数据块的顺序，存储器设备可以为至少两个数据块生成预取信息。

公开(公告)号：US20150082068A1

公开(公告)日：2015-03-19

申请号：US14551995

申请日：2014-11-24

Applicant: Microsoft Technology Licensing, LLC

Inventor： Shahram Izadi ,  Behrooz Chitsaz

IPC: G06F1/32 ,  G06F1/16 ,  G06F12/08 ,  G06F17/24

CPC classification number: H04L67/2842 ,  G06F1/1626 ,  G06F1/1647 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0873 ,  G06F17/241 ,  G06F2200/1637 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  Y02D10/122

Abstract: A dual-mode, dual-display shared resource computing (SRC) device is usable to stream SRC content from a host SRC device while in an on-line mode and maintain functionality with the content during an off-line mode. Such remote SRC devices can be used to maintain multiple user-specific caches and to back-up cached content for multi-device systems.

Abstract translation: 双模式双显示共享资源计算（SRC）设备可用于在处于在线模式的情况下从主机SRC设备流式传输SRC内容，并且在离线模式期间保持内容的功能。 这样的远程SRC设备可用于维护多个用户特定的高速缓存以及备份多设备系统的缓存内容。

公开(公告)号：US20100122264A1

公开(公告)日：2010-05-13

申请号：US12317854

申请日：2008-12-30

Applicant: Zhou Xiaocheng ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

Inventor： Zhou Xiaocheng ,  Shoumeng Yan ,  Ying Gao ,  Hu Chen ,  Peinan Zhang ,  Mohan Rajagopalan ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/00 ,  G06F13/14

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide language support for CPU-GPU platforms. In one embodiment, code can be flexibly executed on both the CPU and GPU. CPU code can offload a kernel to the GPU. That kernel may in turn call preexisting libraries on the CPU, or make other calls into CPU functions. This allows an application to be built without requiring the entire call chain to be recompiled. Additionally, in one embodiment data may be shared seamlessly between CPU and GPU. This includes sharing objects that may have virtual functions. Embodiments thus ensure the right virtual function gets invoked on the CPU or the GPU if a virtual function is called by either the CPU or GPU.

Abstract translation: 本发明的实施例为CPU-GPU平台提供语言支持。 在一个实施例中，可以在CPU和GPU两者上灵活地执行代码。 CPU代码可以将内核卸载到GPU。 该内核可能会调用CPU上的预先存在的库，或者调用其他CPU函数。 这允许构建应用程序，而不需要重新编译整个调用链。 此外，在一个实施例中，数据可以在CPU和GPU之间无缝共享。 这包括共享可能具有虚拟功能的对象。 因此，如果CPU或GPU调用虚拟功能，这些实施例可以确保在CPU或GPU上调用正确的虚拟功能。

公开(公告)号：US20190239384A1

公开(公告)日：2019-08-01

申请号：US15885054

申请日：2018-01-31

Applicant: DELL PRODUCTS L.P.

Inventor： Travis C. North ,  Karunakar P. Reddy

IPC: H05K7/20 ,  F04D29/70 ,  G01L19/00 ,  G06F1/20

CPC classification number: H05K7/20209 ,  F04D29/703 ,  G01L19/0092 ,  G01L2019/0053 ,  G06F1/203 ,  G06F2212/161 ,  H05K7/20136

Abstract: Systems and methods are provided that that may be implemented to detect impeded flow of cooling air within a chassis enclosure of an information handling system based on sensed air pressure and/or air pressure changes occurring within the cooling air flow while the system is actively running. The systems and methods may be further implemented to take one or more thermal management actions based on sensed air pressure within the chassis enclosure together with other optional sensed parameters (e.g., such as sensed temperatures and/or sensed user operating mode based on accelerometer and/or gyroscope sensor input).

公开(公告)号：US09588826B2

公开(公告)日：2017-03-07

申请号：US14566654

申请日：2014-12-10

Applicant: Intel Corporation

Inventor： Hu Chen ,  Ying Gao ,  Xiaocheng Zhou ,  Shoumeng Yan ,  Peinan Zhang ,  Mohan Rajagopalan ,  Jesse Fang ,  Avi Mendelson ,  Bratin Saha

IPC: G06F9/54 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06T1/20 ,  G06T1/60

CPC classification number: G06F9/544 ,  G06F12/0815 ,  G06F12/084 ,  G06F12/1009 ,  G06F12/1063 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/109 ,  G06F2212/161 ,  G06F2212/622 ,  G06F2212/656 ,  G06F2212/657 ,  G06F2212/682 ,  G06T1/20 ,  G06T1/60

Abstract: Embodiments of the invention provide a programming model for CPU-GPU platforms. In particular, embodiments of the invention provide a uniform programming model for both integrated and discrete devices. The model also works uniformly for multiple GPU cards and hybrid GPU systems (discrete and integrated). This allows software vendors to write a single application stack and target it to all the different platforms. Additionally, embodiments of the invention provide a shared memory model between the CPU and GPU. Instead of sharing the entire virtual address space, only a part of the virtual address space needs to be shared. This allows efficient implementation in both discrete and integrated settings.

Abstract translation: 本发明的实施例提供了一种用于CPU-GPU平台的编程模型。 特别地，本发明的实施例为集成和分立设备提供统一的编程模型。 该模型还适用于多个GPU卡和混合GPU系统（分立和集成）。 这允许软件供应商编写单个应用程序堆栈并将其定位到所有不同的平台。 另外，本发明的实施例提供了CPU和GPU之间的共享存储器模型。 而不是共享整个虚拟地址空间，只需要共享虚拟地址空间的一部分。 这允许在离散和集成设置中有效实现。

公开(公告)号：US09552036B2

公开(公告)日：2017-01-24

申请号：US14551995

申请日：2014-11-24

Applicant: Microsoft Technology Licensing, LLC.

Inventor： Shahram Izadi ,  Behrooz Chitsaz

IPC: G06F12/00 ,  G06F13/00 ,  G06F1/32 ,  G06F1/16 ,  G06F12/08 ,  G06F17/24

CPC classification number: H04L67/2842 ,  G06F1/1626 ,  G06F1/1647 ,  G06F1/3203 ,  G06F1/3293 ,  G06F1/3296 ,  G06F12/0811 ,  G06F12/0813 ,  G06F12/0873 ,  G06F17/241 ,  G06F2200/1637 ,  G06F2212/154 ,  G06F2212/161 ,  G06F2212/284 ,  G06F2212/3042 ,  G06F2212/305 ,  Y02D10/122

Abstract: A dual-mode, dual-display shared resource computing (SRC) device is usable to stream SRC content from a host SRC device while in an on-line mode and maintain functionality with the content during an off-line mode. Such remote SRC devices can be used to maintain multiple user-specific caches and to back-up cached content for multi-device systems.

Abstract translation: 双模式双显示共享资源计算（SRC）设备可用于在处于在线模式的情况下从主机SRC设备流式传输SRC内容，并且在离线模式期间保持内容的功能。 这样的远程SRC设备可用于维护多个用户特定的高速缓存以及备份多设备系统的缓存内容。