公开(公告)号：US12211583B2

公开(公告)日：2025-01-28

申请号：US18021442

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  Shahram Nikoukary ,  Catherine Chen

IPC: G11C5/02 ,  G11C7/10 ,  G11C7/22

Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

公开(公告)号：US20230298642A1

公开(公告)日：2023-09-21

申请号：US18021442

申请日：2021-08-24

Applicant: Rambus Inc.

Inventor： Torsten Partsch ,  Shahram Nikoukary ,  Catherine Chen

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1084 ,  G11C7/1057 ,  G11C7/222

Abstract: In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

公开(公告)号：US11762787B2

公开(公告)日：2023-09-19

申请号：US17433071

申请日：2020-02-18

Applicant: Rambus Inc.

Inventor： Steven C. Woo ,  Torsten Partsch

IPC: G06F13/16

CPC classification number: G06F13/1668

Abstract: A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

公开(公告)号：US20230009384A1

公开(公告)日：2023-01-12

申请号：US17852165

申请日：2022-06-28

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G06F13/16 ,  G11C7/06 ,  H01L25/065

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US20240345735A1

公开(公告)日：2024-10-17

申请号：US18681716

申请日：2022-08-08

Applicant: Rambus Inc.

Inventor： Brent Steven Haukness ,  Christopher Haywood ,  Torsten Partsch ,  Thomas Vogelsang

IPC: G06F3/06

CPC classification number: G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

Abstract: Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM storage cells organized into bank groups. Each bank group includes multiple banks, where each of the multiple banks includes addressable columns of DRAM storage cells. The DRAM device includes signal interface circuitry having dedicated write data path circuitry and dedicated read data path circuitry. Selector circuitry, for a first memory transaction, selectively couples at least one of the addressable columns of DRAM storage cells to the dedicated read data path circuitry or the dedicated write data path circuitry.

公开(公告)号：US20240127903A1

公开(公告)日：2024-04-18

申请号：US18474643

申请日：2023-09-26

Applicant: Rambus Inc.

Inventor： Thomas Vogelsang ,  Torsten Partsch

IPC: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

CPC classification number: G11C29/52 ,  G11C11/4091 ,  G11C11/4096

Abstract: A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

公开(公告)号：US20220283743A1

公开(公告)日：2022-09-08

申请号：US17637724

申请日：2020-08-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G06F3/06

Abstract: Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) dynamic random access memory (DRAM) device is disclosed. The IC DRAM device includes memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address. A command/address (C/A) interface receives C/A information defining a joint command. The joint command includes information specifying a first memory access operation, a first bank group address associated with the first memory access operation, and a second memory access operation to be automatically directed to the first bank group address.

公开(公告)号：US20220199132A1

公开(公告)日：2022-06-23

申请号：US17432064

申请日：2020-02-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

公开(公告)号：US20190220222A1

公开(公告)日：2019-07-18

申请号：US16329051

申请日：2017-07-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Torsten Partsch

IPC: G06F3/06 ,  G11C7/10 ,  G11C7/06 ,  G11C7/22 ,  H01L25/065 ,  G06F13/16

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679 ,  G06F13/1668 ,  G06F2213/16 ,  G11C7/06 ,  G11C7/1015 ,  G11C7/1057 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/1087 ,  G11C7/1093 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/4096 ,  G11C2207/107 ,  G11C2207/2272 ,  G11C2207/2281 ,  G11C2207/229 ,  H01L25/0657 ,  H01L2225/06541

Abstract: First data is read out of a core storage array of a memory component over a first time interval constrained by data output bandwidth of the core storage array. After read out from the core storage array, the first data is output from the memory component over a second time interval that is shorter than the first time interval and that corresponds to a data transfer bandwidth greater than the data output bandwidth of the core storage array.

公开(公告)号：US12230362B2

公开(公告)日：2025-02-18

申请号：US18646059

申请日：2024-04-25

Applicant: Rambus Inc.

Inventor： Torsten Partsch

IPC: G11C7/22

Abstract: In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.