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17 条记录 (耗时 0.016 秒)

    DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER
    1.
    发明公开
    DATA-BUFFER CONTROLLER/CONTROL-SIGNAL REDRIVER 审中-公开

    公开(公告)号：US20230298642A1

    公开(公告)日：2023-09-21

    申请号：US18021442

    申请日：2021-08-24

    申请人： Rambus Inc.

    发明人： Torsten Partsch ,  Shahram Nikoukary ,  Catherine Chen

    IPC分类号： G11C7/10 ,  G11C7/22

    CPC分类号： G11C7/1084 ,  G11C7/1057 ,  G11C7/222

    摘要： In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.

    Quad-channel DRAM
    2.
    发明授权
    Quad-channel DRAM 有权

    公开(公告)号：US11762787B2

    公开(公告)日：2023-09-19

    申请号：US17433071

    申请日：2020-02-18

    申请人： Rambus Inc.

    发明人： Steven C. Woo ,  Torsten Partsch

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1668

    摘要： A DRAM includes at least four groups of memory cores and at least four memory access channel interfaces that, in a first mode, each respectively are to receive memory access commands, directed to a corresponding one of the groups of memory cores. One-half of the memory access channel interfaces are to, in a second mode, each respectively receive memory access commands, directed to a corresponding two of four of the groups of memory cores. The memory access channel interfaces to have electrical connection conductors that lie on opposing sides of at least one line of reflectional symmetry from a second one-half of the one-half of the at least four memory access channel interfaces.

    LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH DEDICATED READ-WRITE DATA PATHS
    4.
    发明公开
    LOW LATENCY DYNAMIC RANDOM ACCESS MEMORY (DRAM) ARCHITECTURE WITH DEDICATED READ-WRITE DATA PATHS 审中-公开

    公开(公告)号：US20240345735A1

    公开(公告)日：2024-10-17

    申请号：US18681716

    申请日：2022-08-08

    申请人： Rambus Inc.

    发明人： Brent Steven Haukness ,  Christopher Haywood ,  Torsten Partsch ,  Thomas Vogelsang

    IPC分类号： G06F3/06

    CPC分类号： G06F3/0611 ,  G06F3/0659 ,  G06F3/0673

    摘要： Memory devices, modules, controllers, systems and associated methods are disclosed. In one embodiment, a dynamic random access memory (DRAM) device is disclosed. The DRAM device includes memory core circuitry including an array of DRAM storage cells organized into bank groups. Each bank group includes multiple banks, where each of the multiple banks includes addressable columns of DRAM storage cells. The DRAM device includes signal interface circuitry having dedicated write data path circuitry and dedicated read data path circuitry. Selector circuitry, for a first memory transaction, selectively couples at least one of the addressable columns of DRAM storage cells to the dedicated read data path circuitry or the dedicated write data path circuitry.

    DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING
    5.
    发明公开
    DYNAMIC, RANDOM-ACCESS MEMORY WITH HIDDEN MEMORY SCRUBBING 审中-公开

    公开(公告)号：US20240127903A1

    公开(公告)日：2024-04-18

    申请号：US18474643

    申请日：2023-09-26

    申请人： Rambus Inc.

    发明人： Thomas Vogelsang ,  Torsten Partsch

    IPC分类号： G11C29/52 ,  G11C11/4091 ,  G11C11/4096

    CPC分类号： G11C29/52 ,  G11C11/4091 ,  G11C11/4096

    摘要： A memory includes a local control circuitry that manages scrub transactions using a set of sense amplifiers separate from those used for access (read and write) transactions. The local control circuitry interrupts scrub transactions to prioritize access requests, thereby offering improved memory performance. The local control circuitry also divides scrub transactions into phases and periods based on whether the scrub transaction requires access to bitlines used for read and write access. This division allows the local control circuitry to interleave and interrupt scrub transactions with access transactions in a manner that minimizes access interference.

    JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND METHODS
    6.
    发明申请
    JOINT COMMAND DYNAMIC RANDOM ACCESS MEMORY (DRAM) APPARATUS AND METHODS 有权

    公开(公告)号：US20220283743A1

    公开(公告)日：2022-09-08

    申请号：US17637724

    申请日：2020-08-25

    申请人： Rambus Inc.

    发明人： Torsten Partsch

    IPC分类号： G06F3/06

    摘要： Memory controllers, devices, modules, systems and associated methods are disclosed. In one embodiment, an integrated circuit (IC) dynamic random access memory (DRAM) device is disclosed. The IC DRAM device includes memory core circuitry organized into bank groups of storage cells, each bank group accessible via a corresponding bank group address. A command/address (C/A) interface receives C/A information defining a joint command. The joint command includes information specifying a first memory access operation, a first bank group address associated with the first memory access operation, and a second memory access operation to be automatically directed to the first bank group address.

    LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST
    7.
    发明申请
    LOW POWER MEMORY WITH ON-DEMAND BANDWIDTH BOOST 有权

    公开(公告)号：US20220199132A1

    公开(公告)日：2022-06-23

    申请号：US17432064

    申请日：2020-02-25

    申请人： Rambus Inc.

    发明人： Torsten Partsch

    IPC分类号： G11C7/22

    摘要： In a memory component having a command/address interface, timing interface and data interface, the command/address interface receives a first command/address value from a control component during a first interval and a second command/address value from the control component during a second interval. The timing interface receives a data strobe from the control component during the first interval and a data clock from the control component during the second interval, the data strobe departing from a parked voltage level to commence toggling at a time corresponding to reception of the first command/address value, and the data clock toggling throughout the second interval regardless of second command/address value reception-time. The data interface samples first write data corresponding to the first command/address value at times indicated by toggling of the data strobe, and samples second write data corresponding to the second command/address value at times indicated by toggling of the data clock.

    Buffered dynamic random access memory device
    10.
    发明授权
    Buffered dynamic random access memory device 有权

    公开(公告)号：US12002506B2

    公开(公告)日：2024-06-04

    申请号：US17728638

    申请日：2022-04-25

    申请人： Rambus Inc.

    发明人： Torsten Partsch

    IPC分类号： G11C11/00 ,  G11C11/4076 ,  G11C11/4093 ,  G11C11/4096

    CPC分类号： G11C11/4096 ,  G11C11/4076 ,  G11C11/4093

    摘要： A DRAM device may be configured to retransmit or not retransmit zero or more of command/address signals, write data signals, read data signals, and/or data strobe signals. The DRAM device may have separate, unidirectional read data signal and write data signal interfaces. Combined activate and read or write commands may be implemented. The configuration of the DRAM to retransmit or not retransmit signals may be determined by the DRAM device's physical location on a module via hardwired configuration pins. The various configurations allows a DRAM device to be used on both a long and narrow form factor module and a DIMM module.