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公开(公告)号：US11953981B2
公开(公告)日：2024-04-09
申请号：US18092556
申请日：2023-01-03
申请人： Rambus Inc.
CPC分类号： G06F11/079 , G06F11/073 , G06F11/0772 , G06F13/00 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US11809345B2
公开(公告)日：2023-11-07
申请号：US17677714
申请日：2022-02-22
申请人： Rambus Inc.
CPC分类号： G06F13/1689 , G06F13/1673 , G06F13/1678 , G06F13/4022 , G06F13/4265
摘要： A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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3.发明申请公开(公告)号：US20210049119A1
公开(公告)日：2021-02-18
申请号：US17021024
申请日：2020-09-15
申请人： Rambus Inc.
摘要： A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US10146608B2
公开(公告)日：2018-12-04
申请号：US15090399
申请日：2016-04-04
申请人： Rambus Inc.
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20230298642A1
公开(公告)日：2023-09-21
申请号：US18021442
申请日：2021-08-24
申请人： Rambus Inc.
CPC分类号： G11C7/1084 , G11C7/1057 , G11C7/222
摘要： In a memory system having multiple memory sockets for removable insertion of memory modules therein, off-module data buffers are disposed in a data signaling data path between a memory control component and the memory sockets, and an off-module buffer controller is disposed in a control signaling path between the memory control component and the memory sockets. The off-module buffer controller receives control signals transmitted by the memory control component and re-drives/re-transmits the control signals to the memory sockets. The off-module buffer controller generates buffer-control signals in response to the control signals and outputs the buffer-control signals to the off-module data buffers to multiplex host-control-component access to the memory sockets.
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公开(公告)号：US11573849B2
公开(公告)日：2023-02-07
申请号：US17236445
申请日：2021-04-21
申请人： Rambus Inc.
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
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公开(公告)号：US20220245073A1
公开(公告)日：2022-08-04
申请号：US17677714
申请日：2022-02-22
申请人： Rambus Inc.
摘要： A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US20160293239A1
公开(公告)日：2016-10-06
申请号：US15090399
申请日：2016-04-04
申请人： Rambus Inc.
CPC分类号： G06F11/079 , G06F11/073 , G06F11/0772 , G11C5/04 , G11C7/20 , G11C8/12 , G11C29/26 , G11C29/44
摘要： During system initialization, each data buffer device and/or memory device on a memory module is configured with a unique (at least to the module) device identification number. In order to access a single device (rather than multiple buffers and/or memory devices), a target identification number is written to all of the devices using a command bus connected to all of the data buffer devices or memory devices, respectively. The devices whose respective device identification numbers do not match the target identification number are configured to ignore future command bus transactions (at least until the debug mode is turned off.) The selected device that is configured with a device identification number matching the target identification number is configured to respond to command bus transactions.
摘要翻译： 在系统初始化期间，存储器模块上的每个数据缓冲设备和/或存储器设备被配置为唯一（至少对于模块）设备标识号。 为了访问单个设备（而不是多个缓冲器和/或存储设备），使用分别连接到所有数据缓冲设备或存储设备的命令总线将目标识别号码写入所有设备。 各个设备标识号与目标识别号码不一致的设备被配置为忽略未来的命令总线事务（至少直到调试模式被关闭）。所选择的设备被配置有与目标识别号码相匹配的设备标识号 被配置为响应命令总线事务。
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9.发明公开公开(公告)号：US20240095198A1
公开(公告)日：2024-03-21
申请号：US18480344
申请日：2023-10-03
申请人： Rambus Inc.
CPC分类号： G06F13/1689 , G06F13/1673 , G06F13/1678 , G06F13/4022 , G06F13/4265
摘要： A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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公开(公告)号：US11275702B2
公开(公告)日：2022-03-15
申请号：US17021024
申请日：2020-09-15
申请人： Rambus Inc.
摘要： A memory system supports single- and dual-memory-module configurations, both supporting point-to-point communication between a host (e.g., a memory controller) and the memory module or modules. Each memory module includes an address-buffer component, data-buffer components, and two sets of memory dies, each set termed a “timing rank,” that can be accessed independently. The one memory module is configured in a wide mode for the single-memory-module configuration, in which case both timing ranks work together, as a “package rank,” to communicate full-width data. Each of two memory modules are configured in a narrow mode for the dual-memory-module configuration, in which case one timing rank from each memory module communicates data in parallel to appear to the host as single package ranks. The data-buffer components support separate and configurable write and read delays for the different timing ranks on each module to provide read and write leveling within and between memory modules.
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