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    Hybrid memory system with increased bandwidth
    1.
    发明授权
    Hybrid memory system with increased bandwidth 有权

    公开(公告)号：US12073901B2

    公开(公告)日：2024-08-27

    申请号：US17658846

    申请日：2022-04-12

    申请人： QUALCOMM Incorporated

    发明人： Jungwon Suh

    IPC分类号： G11C29/42 ,  G11C7/10 ,  G11C8/18 ,  G11C29/12

    CPC分类号： G11C29/42 ,  G11C7/1048 ,  G11C7/1063 ,  G11C8/18 ,  G11C29/1201

    摘要： A hybrid memory system with improved bandwidth is disclosed. In one aspect, a memory system is provided that increases bandwidth relative to the JEDEC low-power double data rate version 5 (LPDDR5) standard. This improvement is made possible by increasing a data conductor count from sixteen to twenty-four. Optionally, the bandwidth may be further improved by increasing a clock frequency from a first value to a second value. This allows the hybrid memory system to provide improved bandwidth without the complications of merely doubling pin counts or doubling clock speed. Further, coding techniques tailored to the pin count and pin layout are provided.

    Memory system with adaptive refresh
    2.
    发明授权
    Memory system with adaptive refresh 有权

    公开(公告)号：US12038855B2

    公开(公告)日：2024-07-16

    申请号：US17650455

    申请日：2022-02-09

    申请人： QUALCOMM Incorporated

    发明人： Pankaj Deshmukh ,  Shyamkumar Thoziyoor ,  Vishakh Balakuntalam Visweswara ,  Jungwon Suh ,  Subbarao Palacharla

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1668

    摘要： A memory system with adaptive refresh commands is disclosed. In one aspect, a memory system or device that has multiple banks within a channel may receive a per bank command that indicates a first bank to be refreshed and provides additional information about a second bank to be refreshed. In a further exemplary aspect, a quad bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through fourth banks to be refreshed. In a further exemplary aspect, an octa bank refresh command may be sent that indicates a first bank to be refreshed and provides additional information about second through eighth banks to be refreshed. The three new refresh commands allow adjacent or spaced banks to be refreshed.

    Enhanced data clock operations in memory
    4.
    发明授权
    Enhanced data clock operations in memory 有权

    公开(公告)号：US11175836B2

    公开(公告)日：2021-11-16

    申请号：US16803977

    申请日：2020-02-27

    申请人： Qualcomm Incorporated

    发明人： Jungwon Suh ,  Dexter Tamio Chun ,  Michael Hawjing Lo ,  Shyamkumar Thoziyoor ,  Ravindra Kumar

    IPC分类号： G06F3/06 ,  G06F12/0875

    摘要： Methods and apparatuses for improve data clock to reduce power consumption are presented. The apparatus includes a memory configured to receive a data clock from a host via a link and to synchronize the data clock with the host. The memory includes a clock tree buffer configured to toggle based on the data clock to capture write data or to output read data and a command decoder configured to detect a data clock suspend command while the data clock is synchronized between the host and the memory. The clock tree buffer is configured to disable toggling based on the data clock in response to the command decoder detecting the data clock suspend command. the host includes a memory controller configured to provide a data clock suspend command to the memory via the link while the data clock is synchronized between the host and the memory.

    Partial refresh technique to save memory refresh power
    5.
    发明授权
    Partial refresh technique to save memory refresh power 有权

    公开(公告)号：US10726904B2

    公开(公告)日：2020-07-28

    申请号：US16362427

    申请日：2019-03-22

    申请人： QUALCOMM Incorporated

    发明人： Jungwon Suh ,  Yanru Li ,  Michael Hawjing Lo ,  Dexter Tamio Chun

    IPC分类号： G11C13/06 ,  G11C11/406 ,  G11C7/10 ,  G11C8/12

    摘要： In a conventional memory subsystem, a memory controller issues explicit refresh commands to a DRAM memory device to maintain integrity of the data stored in the memory device when the memory device is in an auto-refresh mode. A significant amount of power may be consumed to carry out the refresh. To address this and other issues, it is proposed to allow a partial refresh in the auto-refresh mode in which the refreshing operation may be skipped for a subset of the memory cells. Through such selective refresh skipping, the power consumed for auto-refreshes may be reduced. Operating system kernels and memory drivers may be configured to determine areas of memory for which the refreshing operation can be skipped.

    LOW POWER DATA TRANSFER FOR MEMORY SUBSYSTEM
    6.
    发明申请
    LOW POWER DATA TRANSFER FOR MEMORY SUBSYSTEM 审中-公开

    公开(公告)号：US20180052785A1

    公开(公告)日：2018-02-22

    申请号：US15243435

    申请日：2016-08-22

    申请人： QUALCOMM Incorporated

    发明人： Jungwon Suh ,  Dexter Chun ,  Haw-Jing Lo

    IPC分类号： G06F13/16

    CPC分类号： G06F13/1668 ,  G06F13/1673 ,  Y02D10/14

    摘要： Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

    Methods and apparatuses for in-system field repair and recovery from memory failures
    9.
    发明授权
    Methods and apparatuses for in-system field repair and recovery from memory failures 有权
    从内存故障中进行现场维修和恢复的方法和设备

    公开(公告)号：US09274715B2

    公开(公告)日：2016-03-01

    申请号：US13957476

    申请日：2013-08-02

    申请人： QUALCOMM Incorporated

    发明人： Dexter T. Chun ,  Jungwon Suh ,  Stephen A. Molloy ,  Jung Pill Kim

    IPC分类号： G06F12/10 ,  G06F3/06 ,  G06F11/10 ,  G11C16/34 ,  G06F12/02

    CPC分类号： G06F3/0638 ,  G06F3/0617 ,  G06F3/0683 ,  G06F11/1048 ,  G06F12/0215 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/50016 ,  G11C2029/0409

    摘要： In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

    摘要翻译： 在特定实施例中，设备包括存储器地址重映射电路和重映射引擎。 存储器地址重映射电路包括比较电路，用于将接收到的存储器地址与一个或多个重映射地址进行比较。 存储器地址重映射电路还包括响应于比较电路的输出物理地址的选择电路。 物理地址对应于随机存取存储器（RAM）中的位置。 重映射引擎被配置为响应于检测到特定位置处的错误发生次数满足阈值而更新一个或多个重映射地址以包括特定地址。

    DRAM sub-array level refresh
    10.
    发明授权
    DRAM sub-array level refresh 有权
    DRAM子阵列级刷新

    公开(公告)号：US08982654B2

    公开(公告)日：2015-03-17

    申请号：US14088098

    申请日：2013-11-22

    申请人： QUALCOMM Incorporated

    发明人： Xiangyu Dong ,  Jungwon Suh

    IPC分类号： G11C11/406

    CPC分类号： G11C11/40618 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611

    摘要： A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

    摘要翻译： 耦合到具有多个存储器单元的子阵列的存储器芯片的存储器控​​制器被配置为确定存储器芯片的配置。 存储器控制器被配置为读取存储器芯片的子阵列配置并且检测外部命令和刷新操作之间的子阵列电平冲突。 内存控制器在刷新操作期间保持一个或多个非冲突的页面打开。