公开(公告)号：US09864536B2

公开(公告)日：2018-01-09

申请号：US14062859

申请日：2013-10-24

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Haw-Jing Lo

IPC: G06F3/06 ,  H03M7/40 ,  H03M7/30

CPC classification number: G06F3/0625 ,  G06F3/0644 ,  G06F3/0673 ,  H03M7/40 ,  H03M7/6047

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a system on chip (SoC) and an encoder. The SoC comprises one or more memory clients for accessing a dynamic random access memory (DRAM) memory system coupled to the SoC. The encoder resides on the SoC and is configured to reduce a data activity factor of memory data received from the memory clients by encoding the received memory data according to a compression scheme and providing the encoded memory data to the DRAM memory system. The DRAM memory system is configured to decode the encoded memory data according to the compression scheme into the received memory data.

公开(公告)号：US09383809B2

公开(公告)日：2016-07-05

申请号：US14079620

申请日：2013-11-13

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Haw-Jing Lo

IPC: G06F1/00 ,  G06F1/32 ,  G11C7/10 ,  G11C11/4096 ,  G06F7/76

CPC classification number: G06F1/3275 ,  G06F1/32 ,  G06F1/3253 ,  G06F7/764 ,  G11C7/1006 ,  G11C7/1009 ,  G11C7/1057 ,  G11C7/1084 ,  G11C11/4096

Abstract: Systems and methods are disclosed for reducing memory I/O power. One embodiment is a system comprising a system on chip (SoC), a DRAM memory device, and a data masking power reduction module. The SoC comprises a memory controller. The DRAM memory device is coupled to the memory controller via a plurality of DQ pins. The data masking power reduction module comprises logic configured to drive the DQ pins to a power saving state during a data masking operation.

Abstract translation: 公开了用于降低存储器I / O功率的系统和方法。 一个实施例是包括片上系统（SoC），DRAM存储器件和数据屏蔽功率降低模块的系统。 SoC包括一个内存控制器。 DRAM存储器件通过多个DQ引脚耦合到存储器控制器。 数据屏蔽功率降低模块包括被配置为在数据屏蔽操作期间将DQ引脚驱动到功率节省状态的逻辑。

公开(公告)号：US09104413B2

公开(公告)日：2015-08-11

申请号：US13668865

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

公开(公告)号：US09612648B2

公开(公告)日：2017-04-04

申请号：US13962746

申请日：2013-08-08

Applicant: Qualcomm Incorporated

Inventor： Dexter Chun ,  Yanru Li ,  Alex Tu ,  Haw-Jing Lo

IPC: G06F12/00 ,  G06F1/32 ,  G06F12/06 ,  G11C14/00

CPC classification number: G06F1/3275 ,  G06F12/0607 ,  G06F2212/1028 ,  G11C14/0009 ,  Y02D10/13 ,  Y02D10/14

Abstract: Systems and methods are disclosed for providing memory channel interleaving with selective power or performance optimization. One such method involves configuring a memory address map for two or more memory devices accessed via two or more respective memory channels with an interleaved region and a linear region. The interleaved region comprises an interleaved address space for relatively higher performance use cases. The linear region comprises a linear address space for relatively lower power use cases. Memory requests are received from one or more clients. The memory requests comprise a preference for power savings or performance. Received memory requests are assigned to the linear region or the interleaved region according to the preference for power savings or performance.

公开(公告)号：US09430434B2

公开(公告)日：2016-08-30

申请号：US14033233

申请日：2013-09-20

Applicant: Qualcomm Incorporated

Inventor： Haw-Jing Lo ,  Dexter Chun

IPC: G06F13/16 ,  G06F13/40 ,  G06F1/32

CPC classification number: G06F13/4018 ,  G06F1/3253 ,  G06F1/3275 ,  G06F13/1678 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/151

Abstract: Systems and methods are disclosed for conserving power consumption in a memory system. One such system comprises a DRAM memory system and a system on chip (SoC). The SoC is coupled to the DRAM memory system via a memory bus. The SoC comprises one or more memory controllers for processing memory requests from one or more memory clients for accessing the DRAM memory system. The one or more memory controllers are configured to selectively conserve memory power consumption by dynamically resizing a bus width of the memory bus.

Abstract translation: 公开了用于节省存储器系统中的功耗的系统和方法。 一种这样的系统包括DRAM存储器系统和片上系统（SoC）。 SoC通过存储器总线耦合到DRAM存储器系统。 SoC包括用于处理来自一个或多个存储器客户端的访问DRAM存储器系统的存储器请求的一个或多个存储器控制器。 一个或多个存储器控制器被配置为通过动态地调整存储器总线的总线宽度来选择性地节省存储器功耗。

公开(公告)号：US20180052785A1

公开(公告)日：2018-02-22

申请号：US15243435

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Chun ,  Haw-Jing Lo

IPC: G06F13/16

CPC classification number: G06F13/1668 ,  G06F13/1673 ,  Y02D10/14

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

公开(公告)号：US20150186267A1

公开(公告)日：2015-07-02

申请号：US14142573

申请日：2013-12-27

Applicant: QUALCOMM Incorporated

Inventor： Dexter Tamio Chun ,  Haw-Jing Lo ,  Michael Drop

IPC: G06F12/06

CPC classification number: G06F12/06 ,  G06F1/3225 ,  G06F1/3275 ,  G06F13/1673 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D50/20

Abstract: Aspects include computing devices, systems, and methods for reorganizing the storage of data in memory to energize less than all of the memory devices of a memory module for read or write transactions. The memory devices may be connected to individual select lines such that a re-order logic may determine the memory devices to energize for a transaction according to a re-ordered memory map. The re-order logic may re-order memory addresses such that memory address provided by a processor for a transaction are converted to the re-ordered memory address according to the re-ordered memory map without the processor having to change its memory address scheme. The re-ordered memory map may provide for reduced energy consumption by the memory devices, or a balance of energy consumption and performance speed for latency tolerant processes.

Abstract translation: 方面包括用于重新组织存储器中的数据存储器的计算设备，系统和方法，以激励小于用于读取或写入事务的存储器模块的所有存储器设备。 存储器件可以连接到单独的选择线，使得重新排序逻辑可以根据重新排序的存储器映射来确定存储器件激活事务。 重新排序逻辑可以重新排序存储器地址，使得由处理器为交易提供的存储器地址根据重新排序的存储器映射被转换为重新排序的存储器地址，而处理器不必改变其存储器地址方案。 重新排序的存储器映射可以提供由存储器件减少的能量消耗，或等待容忍过程的能量消耗和性能速度的平衡。

公开(公告)号：US20140129757A1

公开(公告)日：2014-05-08

申请号：US13668865

申请日：2012-11-05

Applicant: QUALCOMM INCORPORATED

Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

公开(公告)号：US10394724B2

公开(公告)日：2019-08-27

申请号：US15243435

申请日：2016-08-22

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter Chun ,  Haw-Jing Lo

IPC: G06F13/00 ,  G06F13/16

Abstract: Systems and method are directed to reducing power consumption of data transfer between a processor and a memory. A data to be transferred on a data bus between the processor and the memory is checked for a first data pattern, and if the first data pattern is present, transfer of the first data pattern is suppressed on the data bus. Instead, a first address corresponding to the first data pattern is transferred on a second bus between the processor and the memory. The first address is smaller than the first data pattern. The processor comprises a processor-side first-in-first-out (FIFO) and the memory comprises a memory-side FIFO, wherein the first data pattern is present at the first address in the processor-side FIFO and at the first address in the memory-side FIFO.

公开(公告)号：US09965220B2

公开(公告)日：2018-05-08

申请号：US15016806

申请日：2016-02-05

Applicant: QUALCOMM Incorporated

Inventor： Olivier Alavoine ,  Sejoong Lee ,  Tauseef Kazi ,  Simon Booth ,  Edoardo Regini ,  Renatas Jakushokas ,  Saurabh Patodia ,  Jeffrey Gemar ,  Haw-Jing Lo ,  Vinod Chamarty ,  Boris Andreev ,  Tao Shen ,  Aravind Bhaskara ,  Wenbiao Wang ,  Stephen Molloy

IPC: G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F3/06

CPC classification number: G06F3/0659 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0673 ,  G06F12/08 ,  Y02D10/13 ,  Y02D10/14

Abstract: Various aspects include methods for managing memory subsystems on a computing device. Various aspect methods may include determining a period of time to force a memory subsystem on the computing device into a low power mode, inhibiting memory access requests to the memory subsystem during the determined period of time, forcing the memory subsystem into the low power mode for the determined period of time, and executing the memory access requests to the memory subsystem inhibited during the determined period of time in response to expiration of the determined period of time.