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    Methods and apparatuses for memory power reduction
    1.
    发明授权
    Methods and apparatuses for memory power reduction 有权
    用于记忆功率降低的方法和装置

    公开(公告)号：US09547361B2

    公开(公告)日：2017-01-17

    申请号：US14700017

    申请日：2015-04-29

    Applicant: QUALCOMM Incorporated

    Inventor： Ali Taha ,  Dexter Tamio Chun

    IPC: G06F1/32 ,  G11C11/40 ,  G11C14/00 ,  G11C11/406

    CPC classification number: G06F1/3275 ,  G06F1/3287 ,  G06F2212/1028 ,  G06F2212/205 ,  G11C11/406 ,  G11C14/0009 ,  G11C14/0054 ,  Y02D10/13 ,  Y02D10/14

    Abstract: Methods and apparatuses for memory power reduction are provided. The apparatus determines whether to store data into a DRAM or an NVRAM during an idle state of a processor based on power consumption by the DRAM in association with refreshing the data in the DRAM and use of the data stored in the DRAM by the processor, based on power consumption by the NVRAM in association with use of the data stored in the NVRAM by the processor, and based on a duty cycle associated with current drawn in a first power state and a second power state in association with the data. The NVRAM is a type of non-volatile random-access memory other than flash memory. The processor stores the data into one of the DRAM or the NVRAM based on the determination whether to store the data in the DRAM or the NVRAM.

    Abstract translation: 提供了用于存储器功率降低的方法和装置。 该设备基于DRAM的功耗与DRAM中的数据相关联以及处理器中存储在DRAM中的数据的使用，确定在处理器的空闲状态期间是否将数据存储到DRAM或NVRAM中 关于由处理器使用存储在NVRAM中的数据以及与数据相关联的与第一功率状态和第二功率状态相关联的电流相关联的占空比，由NVRAM产生的功率消耗。 NVRAM是除闪存之外的一种非易失性随机存取存储器。 基于确定是否将数据存储在DRAM或NVRAM中，处理器将数据存储到DRAM或NVRAM之一中。

    Reducing power consumption of volatile memory via use of non-volatile memory
    4.
    发明授权
    Reducing power consumption of volatile memory via use of non-volatile memory 有权

    公开(公告)号：US09891694B2

    公开(公告)日：2018-02-13

    申请号：US13726066

    申请日：2012-12-22

    Applicant: QUALCOMM Incorporated

    Inventor： Ali Taha ,  Vipul Gandhi ,  Phani Babu Giddi

    IPC: G06F1/32 ,  G06F12/02

    CPC classification number: G06F1/3275 ,  G06F1/3206 ,  G06F1/3212 ,  G06F12/0238 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/174 ,  Y02D50/20

    Abstract: A method includes initiating a transition from an operating mode to a sleep mode at an electronic device that includes a volatile memory and a non-volatile memory. In response to the initiating, data is copied from the volatile memory to the non-volatile memory and a portion of the volatile memory is disabled. Another method includes determining that a low performance mode condition is satisfied at an electronic device that includes a volatile memory that stores a first copy of read-only data and a non-volatile memory that stores a second copy of the read-only data. A memory mapping of the read-only data is updated from the volatile memory to the non-volatile memory. A portion of the volatile memory that stores the first copy is disabled and access of the read-only data is directed to the non-volatile memory instead of the volatile memory.

    Method for DSDS/DSDA Idle Power Optimization by Adaptive RF Power Retention and Delta Programming
    6.
    发明申请
    Method for DSDS/DSDA Idle Power Optimization by Adaptive RF Power Retention and Delta Programming 审中-公开
    通过自适应射频功率保持和增量编程实现DSDS / DSDA空闲功率优化的方法

    公开(公告)号：US20150282091A1

    公开(公告)日：2015-10-01

    申请号：US14228618

    申请日：2014-03-28

    Applicant: QUALCOMM Incorporated

    Inventor： Jeremy Huei Lin ,  Rahul Kashyap ,  Ping Zhou ,  RaviTeja Yarra ,  Prashanth Akula ,  Kevin Hsi-huai Wang ,  Anil Satyanarayana Rao ,  Ali Taha ,  Subbarayudu Mutya

    IPC: H04W52/02 ,  H04W24/02

    CPC classification number: H04W52/0274 ,  H04W24/02 ,  H04W52/0258 ,  H04W52/028 ,  H04W88/06 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/1242 ,  Y02D70/1262 ,  Y02D70/142 ,  Y02D70/144 ,  Y02D70/24 ,  Y02D70/26

    Abstract: Various embodiments in the disclosure provide methods implemented by a processor executing on a mobile communication device to dynamically determining whether the power saved by powering down the RF chain between the end of the last reception activities and the beginning of the next reception activities will exceed the power expended to reinitialize the RF chain's components and registers for the next reception activities. Based on this determination, the device processor may configure the RF chain either to power down fully, as in conventional implementations, or to enter a low-power mode in which power is maintained to the power rails supplying the memory registers storing RF communication data, thereby avoiding the power surge of restarting the registers and part of the power drain associated with writing the communication data back into the registers. In some embodiments, the mobile communication device may be a multi-SIM device.

    Abstract translation: 本公开中的各种实施例提供了通过在移动通信设备上执行的处理器来实现的方法，以动态地确定在最后的接收活动的结束和下一个接收活动的开始之间通过断电RF链节省的功率是否将超过功率 用于重新初始化RF链的组件和注册表，用于下一个接收活动。 基于该确定，设备处理器可以将RF链配置为完全断电，如在常规实施中一样，或者进入其中向提供存储RF通信数据的存储器寄存器的电力轨道供电的低功率模式， 从而避免重新启动寄存器的电源浪涌和与将通信数据写入寄存器相关联的部分功耗。 在一些实施例中，移动通信设备可以是多SIM设备。

    System and method for dynamic memory power management
    7.
    发明授权
    System and method for dynamic memory power management 有权
    动态内存电源管理系统和方法

    公开(公告)号：US09104413B2

    公开(公告)日：2015-08-11

    申请号：US13668865

    申请日：2012-11-05

    Applicant: QUALCOMM Incorporated

    Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

    IPC: G06F1/32 ,  G06F12/02

    CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

    Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

    SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT
    8.
    发明申请
    SYSTEM AND METHOD FOR DYNAMIC MEMORY POWER MANAGEMENT 有权
    动态记忆功率管理系统与方法

    公开(公告)号：US20140129757A1

    公开(公告)日：2014-05-08

    申请号：US13668865

    申请日：2012-11-05

    Applicant: QUALCOMM INCORPORATED

    Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

    IPC: G06F12/10 ,  G06F12/02

    CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

    Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

    Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

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