公开(公告)号：US10067865B2

公开(公告)日：2018-09-04

申请号：US14744831

申请日：2015-06-19

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato K. De ,  Richard A. Stewart ,  Gheorghe Calin Cascaval ,  Dexter T. Chun

IPC: G06F12/00 ,  G06F12/02 ,  G06F12/06 ,  G11C7/10

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

公开(公告)号：US09274715B2

公开(公告)日：2016-03-01

申请号：US13957476

申请日：2013-08-02

Applicant: QUALCOMM Incorporated

Inventor： Dexter T. Chun ,  Jungwon Suh ,  Stephen A. Molloy ,  Jung Pill Kim

IPC: G06F12/10 ,  G06F3/06 ,  G06F11/10 ,  G11C16/34 ,  G06F12/02

CPC classification number: G06F3/0638 ,  G06F3/0617 ,  G06F3/0683 ,  G06F11/1048 ,  G06F12/0215 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/349 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/50016 ,  G11C2029/0409

Abstract: In a particular embodiment, a device includes memory address remapping circuitry and a remapping engine. The memory address remapping circuitry includes a comparison circuit to compare a received memory address to one or more remapped addresses. The memory address remapping circuitry also includes a selection circuit responsive to the comparison circuit to output a physical address. The physical address corresponds to a location in a random-access memory (RAM). The remapping engine is configured to update the one or more remapped addresses to include a particular address in response to detecting that a number of occurrences of errors at a particular location satisfies a threshold.

Abstract translation: 在特定实施例中，设备包括存储器地址重映射电路和重映射引擎。 存储器地址重映射电路包括比较电路，用于将接收到的存储器地址与一个或多个重映射地址进行比较。 存储器地址重映射电路还包括响应于比较电路的输出物理地址的选择电路。 物理地址对应于随机存取存储器（RAM）中的位置。 重映射引擎被配置为响应于检测到特定位置处的错误发生次数满足阈值而更新一个或多个重映射地址以包括特定地址。

公开(公告)号：US20150286565A1

公开(公告)日：2015-10-08

申请号：US14744831

申请日：2015-06-19

Applicant: QUALCOMM INCORPORATED

Inventor： Subrato K. De ,  Richard A. Stewart ,  Gheorghe Calin Cascaval ,  Dexter T. Chun

IPC: G06F12/02 ,  G11C7/10

CPC classification number: G06F12/023 ,  G06F12/0607 ,  G06F12/0638 ,  G06F2212/1044 ,  G11C7/1072 ,  Y02D10/13

Abstract: Systems and methods are provided for allocating memory to dissimilar memory devices. An exemplary embodiment includes a method for allocating memory to dissimilar memory devices. An interleave bandwidth ratio is determined, which comprises a ratio of bandwidths for two or more dissimilar memory devices. The dissimilar memory devices are interleaved according to the interleave bandwidth ratio to define two or more memory zones having different performance levels. Memory address requests are allocated to the memory zones based on a quality of service (QoS).

Abstract translation: 提供了系统和方法，用于将存储器分配给不同的存储器件。 示例性实施例包括用于将不同的存储器件分配存储器的方法。 确定交织带宽比，其包括两个或多个不同存储器件的带宽比。 不同的存储器件根据交织带宽比进行交织以定义具有不同性能级别的两个或多个存储器区域。 基于服务质量（QoS）将内存地址请求分配给内存区域。

公开(公告)号：US20140129757A1

公开(公告)日：2014-05-08

申请号：US13668865

申请日：2012-11-05

Applicant: QUALCOMM INCORPORATED

Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

IPC: G06F12/10 ,  G06F12/02

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

公开(公告)号：US09875209B2

公开(公告)日：2018-01-23

申请号：US13887846

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Lalan J. Mishra ,  Dexter T. Chun ,  Animesh Datta

IPC: G06F13/42 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  H04L7/00 ,  H04L25/49

CPC classification number: G06F13/42 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G11C7/10 ,  G11C7/222 ,  H04L7/0008 ,  H04L7/0037 ,  H04L25/4902

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

公开(公告)号：US09448947B2

公开(公告)日：2016-09-20

申请号：US13752427

申请日：2013-01-29

Applicant: QUALCOMM Incorporated

Inventor： Jungwon Suh ,  Dexter T. Chun

IPC: G06F12/10 ,  G11C5/04 ,  G11C5/06 ,  G11C7/02 ,  G11C7/22 ,  H01L25/065 ,  H01L25/10

CPC classification number: G11C5/06 ,  G11C5/04 ,  G11C5/063 ,  G11C7/02 ,  G11C7/222 ,  H01L25/0657 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15311

Abstract: In an embodiment, a stacked package-on-package system has a memory die and a logic die. The memory die comprises a first memory and a second memory, each operated independently of the other, and each having an inter-chip interface electrically connected to the logic die. The logic die has two independent clock sources, one to provide a first clock signal to the first memory, and the other clock source to provide a second clock signal to the second memory.

Abstract translation: 在一个实施例中，堆叠封装的封装系统具有存储器管芯和逻辑管芯。 存储器管芯包括第一存储器和第二存储器，每个存储器和第二存储器分别独立于另一个存储器和第二存储器，并且每个具有电连接到逻辑管芯的芯片间接口。 逻辑管芯具有两个独立的时钟源，一个用于向第一存储器提供第一时钟信号，另一个时钟源提供第二时钟信号给第二存储器。

公开(公告)号：US09110795B2

公开(公告)日：2015-08-18

申请号：US13781320

申请日：2013-02-28

Applicant: QUALCOMM Incorporated

Inventor： Richard A. Stewart ,  Dexter T. Chun

IPC: G06F12/00 ,  G06F12/06 ,  G06F13/16

CPC classification number: G06F12/0607 ,  G06F13/1647

Abstract: Systems and methods are provided for dynamically allocating a memory subsystem. An exemplary embodiment comprises a method for dynamically allocating a memory subsystem in a portable computing device. The method involves fully interleaving a first portion of a memory subsystem having memory components with asymmetric memory capacities. A second remaining portion of the memory subsystem is partial interleaved according to an interleave bandwidth ratio. The first portion of the memory subsystem is allocated to one or more high-performance memory clients. The second remaining portion is allocated to one or more relatively lower-performance memory clients.

Abstract translation: 提供了用于动态分配存储器子系统的系统和方法。 示例性实施例包括用于在便携式计算设备中动态分配存储器子系统的方法。 该方法涉及完全交织具有具有非对称存储器容量的存储器组件的存储器子系统的第一部分。 存储器子系统的第二剩余部分根据交织带宽比被部分交织。 内存子系统的第一部分被分配给一个或多个高性能内存客户端。 第二剩余部分被分配给一个或多个相对较低性能的存储器客户端。

公开(公告)号：US09104413B2

公开(公告)日：2015-08-11

申请号：US13668865

申请日：2012-11-05

Applicant: QUALCOMM Incorporated

Inventor： Haw-Jing Lo ,  Ali Taha ,  Dexter T. Chun

IPC: G06F1/32 ,  G06F12/02

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F12/023 ,  Y02D10/14 ,  Y02D50/20

Abstract: Various embodiments of methods and systems for hardware (“HW”) based dynamic memory management in a portable computing device (“PCD”) are disclosed. One exemplary method includes generating a lookup table (“LUT”) to track each memory page located across multiple portions of a volatile memory. The records in the LUT are updated to keep track of data locations. When the PCD enters a sleep state to conserve energy, the LUT may be queried to determine which specific memory pages in a first portion of volatile memory (e.g., an upper bank) contain data content and which pages in a second portion of volatile memory (e.g., a lower bank) are available for receipt of content. Based on the query, the location of the data in the memory pages of the upper bank is known and can be quickly migrated to memory pages in the lower bank which are identified for receipt of the data.

Abstract translation: 公开了用于便携式计算设备（“PCD”）中基于硬件（“HW”）的动态存储器管理的方法和系统的各种实施例。 一个示例性方法包括生成查找表（“LUT”）以跟踪位于易失性存储器的多个部分上的每个存储器页面。 更新LUT中的记录以跟踪数据位置。 当PCD进入睡眠状态以节省能量时，可以查询LUT以确定易失性存储器（例如，上部存储体）的第一部分中的哪些特定存储器页面包含数据内容以及易失性存储器的第二部分中的哪些页面 例如，较低的银行）可用于接收内容。 基于该查询，数据在上部存储器页面中的位置是已知的，并且可以被快速迁移到被识别用于接收数据的下部的存储器页面中。

公开(公告)号：US20140330994A1

公开(公告)日：2014-11-06

申请号：US13887846

申请日：2013-05-06

Applicant: QUALCOMM INCORPORATED

Inventor： Lalan J. Mishra ,  Dexter T. Chun ,  Animesh Datta

IPC: G06F13/42

CPC classification number: G06F13/42 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G11C7/10 ,  G11C7/222 ,  H04L7/0008 ,  H04L7/0037 ,  H04L25/4902

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.

Abstract translation: 公开了一种基于数据信号占空比和相位调制解调的同步数据链路吞吐量增强技术。 一种方法包括接收要发送的多个比特，对多个比特进行编码以产生表示多个比特的多比特信号，并且在对应于一半的时间段期间经由同步接口发送多比特信号 的同步信号的周期。

公开(公告)号：US09299457B2

公开(公告)日：2016-03-29

申请号：US14187279

申请日：2014-02-23

Applicant: QUALCOMM INCORPORATED

Inventor： Dexter T. Chun ,  Yanru Li ,  Xiangyu Dong ,  Jungwon Suh ,  Jung Pill Kim ,  Deepti Vijayalakshmi Sriramagiri

IPC: G11C29/00 ,  G11C29/44 ,  G06F11/10 ,  G06F11/20 ,  G06F12/02

CPC classification number: G11C29/44 ,  G06F11/1048 ,  G06F11/1076 ,  G06F11/2053 ,  G06F12/0246 ,  G06F2212/7209 ,  G11C2029/4402

Abstract: Systems, methods, and computer programs are disclosed for kernel masking dynamic random access memory (DRAM) defects. One such method comprises: detecting and correcting a single-bit error associated with a physical address in a dynamic random access memory (DRAM); receiving error data associated with the physical address from the DRAM; storing the received error data in a failed address table located in a non-volatile memory; and retiring a kernel page corresponding to the physical address if a number of errors associated with the physical address exceeds an error count threshold.

Abstract translation: 公开了用于内核屏蔽动态随机存取存储器（DRAM）缺陷的系统，方法和计算机程序。 一种这样的方法包括：检测和校正与动态随机存取存储器（DRAM）中的物理地址相关的单位错误; 从DRAM接收与物理地址相关联的错误数据; 将接收到的错误数据存储在位于非易失性存储器中的故障地址表中; 并且如果与物理地址相关联的错误的数量超过错误计数阈值，则退出对应于物理地址的内核页面。