公开(公告)号：US10074609B2

公开(公告)日：2018-09-11

申请号：US15493008

申请日：2017-04-20

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0921 ,  H01L21/823871 ,  H01L23/4824 ,  H01L23/522 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2924/0002 ,  H03K17/168 ,  H03K17/6872 ,  H01L2924/00

Abstract: A first interconnect on an interconnect level connects a first subset of PMOS drains together of a CMOS device. A second interconnect on the interconnect level connects a second subset of the PMOS drains together. The second subset of the PMOS drains is different than the first subset of the PMOS drains. The first interconnect and the second interconnect are disconnected on the interconnect level. A third interconnect on the interconnect level connects a first subset of NMOS drains together of the CMOS device. A fourth interconnect on the interconnect level connects a second subset of the NMOS drains together. The second subset of the NMOS drains is different than the first subset of the NMOS drains. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, and fourth interconnects are coupled together though at least one other interconnect level.

公开(公告)号：US09678154B2

公开(公告)日：2017-06-13

申请号：US14528554

申请日：2014-10-30

Applicant: QUALCOMM Incorporated

Inventor： Animesh Datta ,  Qi Ye ,  Steven James Dillen

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177 ,  H03K5/133 ,  H03K5/134 ,  G11C7/10 ,  G11C29/32 ,  G01R31/3185

CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/32 ,  G11C2029/3202 ,  H03K5/133 ,  H03K5/134

Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

公开(公告)号：US09020084B2

公开(公告)日：2015-04-28

申请号：US13756491

申请日：2013-01-31

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Saravanan Marimuthu ,  Ohsang Kwon

IPC: H04L7/00 ,  H03K3/356

CPC classification number: H04L7/0045 ,  H03K3/356156 ,  H04L7/0037

Abstract: Techniques for resolving a metastable state in a synchronizer are described herein. In one embodiment, a circuit for resolving a metastable state in a synchronizer comprises a signal delay circuit coupled to a node of the synchronizer, wherein the signal delay circuit is configured to delay a data signal at the node to produce a delayed data signal, and a transmission circuit coupled to the signal delay circuit, wherein the transmission circuit is configured to couple the delayed data signal to the node after a delay from a first edge of a clock signal.

Abstract translation: 本文描述了用于解决同步器中的亚稳态的技术。 在一个实施例中，用于分解同步器中的亚稳态的电路包括耦合到同步器的节点的信号延迟电路，其中信号延迟电路被配置为延迟节点处的数据信号以产生延迟的数据信号，以及 耦合到所述信号延迟电路的传输电路，其中所述传输电路被配置为在从时钟信号的第一边缘延迟之后将所述延迟的数据信号耦合到所述节点。

公开(公告)号：US20140306735A1

公开(公告)日：2014-10-16

申请号：US13862015

申请日：2013-04-12

Applicant: QUALCOMM INCORPORATED

Inventor： Seid Hadi Rasouli ,  Animesh Datta ,  Jay Madhukar Shah ,  Martin Saint-Laurent ,  Peeyush Kumar Parkar ,  Sachin Bapat ,  Ramaprasath Vilangudipitchai ,  Mohamed Hassan Abu-Rahma ,  Prayag Bhanubhai Patel

IPC: H03K3/012

CPC classification number: H03K3/012 ,  H03K3/356008 ,  H03K3/35625

Abstract: A circuit including a logic gate responsive to a clock signal and to a control signal. The circuit also includes a master stage of a flip-flop. The circuit further includes a slave stage of the flip-flop responsive to the master stage. The circuit further includes an inverter responsive to the logic gate and configured to output a delayed version of the clock signal. An output of the logic gate and the delayed version of the clock signal are provided to the master stage and to the slave stage of the flip-flop. The master stage is responsive to the control signal to control the slave stage.

Abstract translation: 包括响应于时钟信号和控制信号的逻辑门的电路。 电路还包括触发器的主级。 电路还包括响应于主级的触发器的从级。 电路还包括响应逻辑门并被配置为输出时钟信号的延迟版本的反相器。 逻辑门的输出和时钟信号的延迟版本被提供给主级和触发器的从级。 主级响应控制信号来控制从机级。

公开(公告)号：US10600785B2

公开(公告)日：2020-03-24

申请号：US15927539

申请日：2018-03-21

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Michael Joseph Brunolli ,  Christine Sung-An Hau-Riege ,  Mickael Malabry ,  Sucheta Kumar Harish ,  Prathiba Balasubramanian ,  Kamesh Medisetti ,  Nikolay Bomshtein ,  Animesh Datta ,  Ohsang Kwon

IPC: H01L27/092 ,  H01L21/8238 ,  H03K17/16 ,  H03K17/687 ,  H01L23/482 ,  H01L27/02 ,  H01L23/528 ,  H01L23/522

Abstract: A CMOS device with a plurality of PMOS transistors and a plurality of NMOS transistors includes a first interconnect and a second interconnect on an interconnect level connecting a first subset and a second subset of PMOS drains together, respectively. The first and second subsets are different and the first and second interconnect are disconnected on the interconnect level. A third interconnect and a fourth interconnect on the interconnect level connect a first subset and a second subset of the NMOS drains together, respectively. The third interconnect and the fourth interconnect are disconnected on the interconnect level. The first, second, third, fourth interconnects are coupled together through at least one other interconnect level. Additional interconnects on the interconnect level connect the first and third interconnects together, and the second and fourth interconnects together, to provide parallel current paths with a current path through the at least one other interconnect level.

公开(公告)号：US09577635B2

公开(公告)日：2017-02-21

申请号：US14598182

申请日：2015-01-15

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Steven James Dillen ,  Animesh Datta

IPC: H03K17/687 ,  H03K17/60 ,  H03K19/00

CPC classification number: H03K19/0016 ,  H03K17/6872

Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

Abstract translation: CGC包括使能模块和锁存模块。 启用模块具有使能模块输入和使能模块输出。 锁存模块具有锁存模块输入和锁存模块输出。 锁存模块输入包括用于接收时钟的锁存模块时钟输入和用于接收使能模块输出的锁存模块使能输入。 锁存模块使能输入耦合到使能模块输出。 锁存模块被配置为通过基于使能模块输入的锁存模块输出来启用和禁用时钟。 锁存模块包括作为锁存模块输出的内部使能节点。 锁存模块被配置为使内部使能节点根据使能模块输出和ĒC的功能从低电平转换到高电平，其中E是内部使能节点，C是时钟。

公开(公告)号：US20160124043A1

公开(公告)日：2016-05-05

申请号：US14528554

申请日：2014-10-30

Applicant: QUALCOMM Incorporated

Inventor： Animesh Datta ,  Qi Ye ,  Steven James Dillen

IPC: G01R31/317 ,  G01R31/3177

CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/32 ,  G11C2029/3202 ,  H03K5/133 ,  H03K5/134

Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

Abstract translation: 在一个实施例中，扫描路径中的信号延迟的方法包括以扫描模式延迟扫描路径中的扫描信号，通过将扫描信号传播通过串联耦合的多个延迟器件，其中第一延迟 设备由第一电压供电，延迟装置中的第二个由第二电压供电，第二电压大于第一电压。 该方法还包括在功能模式下禁用延迟设备。

公开(公告)号：US20140124868A1

公开(公告)日：2014-05-08

申请号：US13671114

申请日：2012-11-07

Applicant: QUALCOMM INCORPORATED

Inventor： Pratyush Kamal ,  Esin Terzioglu ,  Foua Vang ,  Prayag Bhanubhai Patel ,  Giridhar Nallapati ,  Animesh Datta

IPC: H01L27/092 ,  H01L29/66

CPC classification number: H01L27/092 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/66545 ,  H01L2027/11831

Abstract: A semiconductor standard cell includes an N-type diffusion area and a P-type diffusion area, both extending across the cell and also outside of the cell. The cell also includes a conductive gate above each diffusion area to create a semiconductive device. A pair of dummy gates are also above the N-type diffusion area and the P-type diffusion area creating a pair of dummy devices. The pair of dummy gates are disposed at opposite edges of the cell. The cell further includes a first conductive line configured to couple the dummy devices to power for disabling the dummy devices.

Abstract translation: 半导体标准单元包括N型扩散区和P型扩散区，两者均延伸穿过电池并且还在电池外部。 电池还包括在每个扩散区域上方的导电栅极以产生半导体器件。 一对虚拟栅极也在N型扩散区域和P型扩散区域之上，形成一对虚设装置。 一对虚拟门设置在电池的相对边缘。 电池还包括第一导线，其被配置为将虚设装置耦合到用于禁用虚设装置的电力。

公开(公告)号：US09979394B2

公开(公告)日：2018-05-22

申请号：US15044988

申请日：2016-02-16

Applicant: QUALCOMM Incorporated

Inventor： Qi Ye ,  Animesh Datta ,  Venkatasubramanian Narayanan ,  Venugopal Boynapalli

IPC: H03K3/356 ,  H03K19/003 ,  H03K3/037 ,  H03K3/033 ,  H03K5/04

CPC classification number: H03K19/00384 ,  H03K3/033 ,  H03K3/0375 ,  H03K5/04

Abstract: The apparatus may include a first latch configured to store a first state or a second state. The first latch may have a first latch input, one of a set input or a reset input, a first pulse clock input, and a first latch output. The first latch input may be coupled to a fixed logic value. The one of the set input or the reset input may be coupled to a clock signal or an inverted clock signal, respectively. The apparatus may include an AND gate having a first AND gate input, a second AND gate input, and a first AND gate output. The clock signal may be coupled to the first AND gate input. The first latch output may be coupled to the second AND gate input. The AND gate output may be configured to output a pulsed clock. The pulsed clock may be coupled to the first pulse clock input.

公开(公告)号：US09875209B2

公开(公告)日：2018-01-23

申请号：US13887846

申请日：2013-05-06

Applicant: QUALCOMM Incorporated

Inventor： Lalan J. Mishra ,  Dexter T. Chun ,  Animesh Datta

IPC: G06F13/42 ,  G11C7/22 ,  G11C7/10 ,  G06F13/16 ,  H04L7/00 ,  H04L25/49

CPC classification number: G06F13/42 ,  G06F13/1689 ,  G06F13/4234 ,  G06F13/4243 ,  G06F13/4282 ,  G11C7/10 ,  G11C7/222 ,  H04L7/0008 ,  H04L7/0037 ,  H04L25/4902

Abstract: A synchronous data-link throughput enhancement technique based on data signal duty-cycle and phase modulation demodulation is disclosed. A method includes receiving multiple bits to be transmitted, encoding the multiple bits to generate a multi-bit signal that represents the multiple bits, and transmitting, via a synchronous interface, the multi-bit signal during a time period that corresponds to one-half of a cycle of a synchronization signal.