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    VOLTAGE COMPARATOR
    1.
    发明申请
    VOLTAGE COMPARATOR 有权
    电压比较器

    公开(公告)号：US20160248414A1

    公开(公告)日：2016-08-25

    申请号：US14818114

    申请日：2015-08-04

    Applicant: QUALCOMM Incorporated

    Inventor： Ramaprasath Vilangudipitchai ,  Dorav Kumar ,  Steven James Dillen ,  Ohsang Kwon ,  Javid Jaffari

    IPC: H03K17/042 ,  H03K5/24

    CPC classification number: H03K17/04206 ,  H03K5/24 ,  H03K5/26 ,  H03K19/0016

    Abstract: Systems and methods for powering up circuits are described herein. In one embodiment, a method for power up comprises comparing a voltage of a first supply rail with a voltage of a second supply rail, and determining whether the voltage of the first supply rail is within a predetermined amount of the voltage of the second supply rail for at least a predetermined period of time based on the comparison. The method also comprises initiating switching of a plurality of switches coupled between the first and second supply rails upon a determination that the voltage of the first supply rail is within the predetermined amount of the voltage of the second supply rail for at least the predetermined period of time.

    Abstract translation: 本文描述了为电路供电的系统和方法。 在一个实施例中，一种用于上电的方法包括将第一电源轨的电压与第二电源轨的电压进行比较，以及确定第一电源轨的电压是否在第二电源轨的电压的预定量内 至少基于该比较的预定时间段。 该方法还包括在确定第一电源轨的电压在第二电源轨的电压的预定量内至少在预定时间段内的情况下，启动耦合在第一和第二电源轨之间的多个开关的开关 时间。

    Clock-gating cell with low area, low power, and low setup time
    3.
    发明授权
    Clock-gating cell with low area, low power, and low setup time 有权
    时钟门控单元，面积小，功耗低，安装时间低

    公开(公告)号：US09577635B2

    公开(公告)日：2017-02-21

    申请号：US14598182

    申请日：2015-01-15

    Applicant: QUALCOMM Incorporated

    Inventor： Seid Hadi Rasouli ,  Steven James Dillen ,  Animesh Datta

    IPC: H03K17/687 ,  H03K17/60 ,  H03K19/00

    CPC classification number: H03K19/0016 ,  H03K17/6872

    Abstract: A CGC includes an enable module and a latch module. The enable module has an enable module input and an enable module output. The latch module has latch module inputs and a latch module output. The latch module inputs include a latch module clock input for receiving a clock and a latch module enable input for receiving the enable module output. The latch module enable input is coupled to the enable module output. The latch module is configured to enable and to disable the clock via the latch module output based on the enable module input. The latch module includes an internal enable node that is the latch module output. The latch module is configured to cause the internal enable node to transition from low to high as a function of the enable module output and ĒC, where E is the internal enable node and C is the clock.

    Abstract translation: CGC包括使能模块和锁存模块。 启用模块具有使能模块输入和使能模块输出。 锁存模块具有锁存模块输入和锁存模块输出。 锁存模块输入包括用于接收时钟的锁存模块时钟输入和用于接收使能模块输出的锁存模块使能输入。 锁存模块使能输入耦合到使能模块输出。 锁存模块被配置为通过基于使能模块输入的锁存模块输出来启用和禁用时钟。 锁存模块包括作为锁存模块输出的内部使能节点。 锁存模块被配置为使内部使能节点根据使能模块输出和ĒC的功能从低电平转换到高电平，其中E是内部使能节点，C是时钟。

    CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN
    4.
    发明申请
    CIRCUIT TECHNIQUES FOR EFFICIENT SCAN HOLD PATH DESIGN 有权
    用于高效扫描路径设计的电路技术

    公开(公告)号：US20160124043A1

    公开(公告)日：2016-05-05

    申请号：US14528554

    申请日：2014-10-30

    Applicant: QUALCOMM Incorporated

    Inventor： Animesh Datta ,  Qi Ye ,  Steven James Dillen

    IPC: G01R31/317 ,  G01R31/3177

    CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/32 ,  G11C2029/3202 ,  H03K5/133 ,  H03K5/134

    Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

    Abstract translation: 在一个实施例中，扫描路径中的信号延迟的方法包括以扫描模式延迟扫描路径中的扫描信号，通过将扫描信号传播通过串联耦合的多个延迟器件，其中第一延迟 设备由第一电压供电，延迟装置中的第二个由第二电压供电，第二电压大于第一电压。 该方法还包括在功能模式下禁用延迟设备。

    Compact design of scan latch
    6.
    发明授权
    Compact design of scan latch 有权
    紧凑型扫描闩锁设计

    公开(公告)号：US09584121B2

    公开(公告)日：2017-02-28

    申请号：US14736213

    申请日：2015-06-10

    Applicant: QUALCOMM Incorporated

    Inventor： Qi Ye ,  Zhengyu Duan ,  Steven James Dillen ,  Animesh Datta

    IPC: H03K3/289 ,  H03K19/00 ,  H03K3/3562

    CPC classification number: H03K19/0013 ,  G01R31/318541 ,  G06F1/04 ,  H03K3/037 ,  H03K3/35625

    Abstract: A MOS device includes a first latch configured with one latch feedback F and configured to receive a latch input I and a latch clock C. The first latch is configured to output Q, where the output Q is a function of CF, IF, and IC, and the latch feedback F is a function of the output Q. The first latch may include a first set of transistors stacked in series in which the first set of transistors includes at least five transistors. The MOS device may further include a second latch coupled to the first latch. The second latch may be configured as a latch in a scan mode and as a pulse latch in a functional mode. The first latch may operate as a master latch and the second latch may operate as a slave latch during the scan mode.

    Abstract translation: MOS器件包括配置有一个锁存器反馈F并被配置为接收锁存器输入I和锁存时钟C的第一锁存器。第一锁存器被配置为输出Q，其中输出Q是CF，IF和IC的函数 并且锁存反馈F是输出Q的函数。第一锁存器可以包括串联堆叠的第一组晶体管，其中第一组晶体管包括至少五个晶体管。 MOS器件还可以包括耦合到第一锁存器的第二锁存器。 第二锁存器可以被配置为扫描模式下的锁存器和功能模式中的脉冲锁存器。 第一锁存器可以作为主锁存器操作，并且第二锁存器可以在扫描模式期间作为从锁存器操作。

    Area-efficient metal-programmable pulse latch design
    7.
    发明授权
    Area-efficient metal-programmable pulse latch design 有权
    区域高效的金属可编程脉冲锁存器设计

    公开(公告)号：US09564881B2

    公开(公告)日：2017-02-07

    申请号：US14720634

    申请日：2015-05-22

    Applicant: QUALCOMM Incorporated

    Inventor： Qi Ye ,  Steven James Dillen ,  Animesh Datta ,  Zhengyu Duan ,  Satyanarayana Sahu ,  Praveen Narendranath

    IPC: H03K3/012 ,  H03K3/037 ,  H03K5/131 ,  H03K5/13

    CPC classification number: H03K3/0375 ,  H03K3/012 ,  H03K3/037 ,  H03K5/131

    Abstract: A pulse generator includes a latch module for storing first/second states, a pulse clock module for generating a clock pulse, and a delay module for delaying the clock pulse at a second latch-module input. The latch module has a first latch-module input coupled to a clock, the second latch-module input, and a latch-module output. The pulse clock module has a first pulse-clock-module input coupled to the clock, a second pulse-clock-module input coupled to the latch-module output, and a pulse-clock-module output. The delay module is coupled between the latch-module output and second pulse-clock-module input or between the pulse-clock-module output and second latch-module input. The delay module provides functionally I1IA at a delay module output, where I1 is a function of I and IA is a function of IN0 and B0, and where I is a delay module input, B0 is a first input bit, and IN0 is a first net input.

    Abstract translation: 脉冲发生器包括用于存储第一/第二状态的锁存模块，用于产生时钟脉冲的脉冲时钟模块以及用于在第二锁存模块输入端延迟时钟脉冲的延迟模块。 锁存模块具有耦合到时钟的第一锁存模块输入端，第二锁存模块输入端和锁存模块输出端。 脉冲时钟模块具有耦合到时钟的第一脉冲时钟模块输入，耦合到锁存模块输出的第二脉冲时钟模块输入和脉冲时钟模块输出。 延迟模块耦合在锁存模块输出和第二个脉冲时钟模块输入之间，或者连接在脉冲时钟模块输出和第二个锁存模块输入之间。 延迟模块在延迟模块输出端提供功能上的I1IA，其中I1是I的函数，IA是IN0和B0的函数，其中I是延迟模块输入，B0是第一个输入位，IN0是第一个 净输入。

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