公开(公告)号：US09812222B2

公开(公告)日：2017-11-07

申请号：US14691570

申请日：2015-04-20

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Dexter Tamio Chun ,  Jungwon Suh ,  Deepti Vijayalakshmi Sriramagiri ,  Yanru Li ,  Mosaddiq Saifuddin ,  Xiangyu Dong

IPC: G06F11/00 ,  G11C29/44 ,  G11C29/00 ,  G06F11/07 ,  G06F11/10 ,  G11C29/42 ,  G11C11/401

CPC classification number: G11C29/4401 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/079 ,  G06F11/0793 ,  G06F11/1048 ,  G11C11/401 ,  G11C29/42 ,  G11C29/76

Abstract: A memory having a redundancy area is operated in a normal mode and an error is detected. A selecting selects between in-line repair process and off-line repair. In-line repair applies a short term error correction, which remaps a fail address to a remapped memory area of the memory. An in-system repair is applied, for a one-time programmed remapping of the fail address to a redundancy area of the memory. In-system repair utilizes idle time of the memory to maintain valid memory content.

公开(公告)号：US09292451B2

公开(公告)日：2016-03-22

申请号：US13769965

申请日：2013-02-19

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong

IPC: G06F12/12 ,  G06F12/08

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/7211

Abstract: Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold.

Abstract translation: 描述了有效的技术来延长具有有限写入耐力的存储器的可用寿命。 高速缓存的磨损均衡技术解决了高速缓存线上的不平衡写入流量，这导致严重写入的高速缓存行比缓存中的其他行失败得快。 每个写入操作一个计数器递增到一个缓存数组。 受当前写入操作影响的一行导致计数器达到阈值的行从缓存中消除而不是将数据写入受影响的行。 可以根据操作程序动态调整阈值。 由于计数器达到阈值，因此停止对当前替换策略指针的更新。

公开(公告)号：US20150092479A1

公开(公告)日：2015-04-02

申请号：US14041868

申请日：2013-09-30

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong

IPC: G11C11/16

CPC classification number: G11C11/1673 ,  G11C7/1075 ,  G11C8/16 ,  G11C11/005 ,  G11C11/16 ,  G11C11/1659 ,  G11C11/56 ,  G11C11/5671 ,  G11C13/0002 ,  G11C17/02 ,  G11C17/14 ,  G11C2213/74 ,  G11C2213/79

Abstract: In a particular embodiment, a device includes a resistance-based memory cell having multiple source lines and multiple access transistors. A coupling configuration of the multiple access transistors to multiple source lines encodes a data value.

Abstract translation: 在特定实施例中，器件包括具有多个源极线和多个存取晶体管的基于电阻的存储单元。 多个存取晶体管与多个源极线的耦合配置对数据值进行编码。

公开(公告)号：US08982654B2

公开(公告)日：2015-03-17

申请号：US14088098

申请日：2013-11-22

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jungwon Suh

IPC: G11C11/406

CPC classification number: G11C11/40618 ,  G06F13/1636 ,  G11C11/406 ,  G11C11/40611

Abstract: A memory controller coupled to a memory chip having a number of sub-arrays of memory cells is configured to determine a configuration of the memory chip. The memory controller is configured to read the sub-array configuration of the memory chip and to detect sub-array level conflicts between external commands and refresh operations. The memory controller keeps one or more non-conflicting pages open during the refresh operations.

Abstract translation: 耦合到具有多个存储器单元的子阵列的存储器芯片的存储器控​​制器被配置为确定存储器芯片的配置。 存储器控制器被配置为读取存储器芯片的子阵列配置并且检测外部命令和刷新操作之间的子阵列电平冲突。 内存控制器在刷新操作期间保持一个或多个非冲突的页面打开。

公开(公告)号：US20140281327A1

公开(公告)日：2014-09-18

申请号：US13842410

申请日：2013-03-15

Applicant: QUALCOMM INCORPORATED

Inventor： Xiangyu Dong ,  Jungwon Suh

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G06F3/061 ,  G06F3/0611 ,  G06F3/0629 ,  G06F12/00 ,  G06F17/5031 ,  G11C11/4076 ,  G11C29/023 ,  G11C29/50012 ,  G11C2029/0409 ,  G11C2207/2254

Abstract: A particular method includes receiving, from a processor, a first memory access request at a memory device. The method also includes processing the first memory access request based on a timing parameter of the memory device. The method further includes receiving, from the processor, a second memory access request at the memory device. The method also includes modifying a timing parameter of the memory device based on addresses identified by the first memory access request and the second memory access request to produce a modified timing parameter. The method further includes processing the second memory access request based on the modified timing parameter.

Abstract translation: 一种特定的方法包括从处理器接收在存储器设备处的第一存储器访问请求。 该方法还包括基于存储器件的定时参数来处理第一存储器访问请求。 该方法还包括从处理器接收在存储器设备处的第二存储器访问请求。 该方法还包括基于由第一存储器访问请求和第二存储器访问请求识别的地址修改存储器件的定时参数以产生修改的定时参数。 该方法还包括基于修改的定时参数来处理第二存储器访问请求。

公开(公告)号：US20140237191A1

公开(公告)日：2014-08-21

申请号：US13769965

申请日：2013-02-19

Applicant: QUALCOMM INCORPORATED

Inventor： Xiangyu Dong

IPC: G06F12/08 ,  G06F12/12

CPC classification number: G06F12/0891 ,  G06F12/0895 ,  G06F12/121 ,  G06F2212/1032 ,  G06F2212/7211

Abstract: Efficient techniques are described for extending the usable lifetime for memories with limited write endurance. A technique for wear-leveling of caches addresses unbalanced write traffic on cache lines which cause heavily written cache lines to fail much fast than other lines in the cache. A counter is incremented for each write operation to a cache array. A line affected by a current write operation which caused the counter to meet a threshold is evicted from the cache rather than writing data to the affected line. A dynamic adjustment of the threshold can be made depending on the operating program. Updates to a current replacement policy pointer are stopped due to the counter meeting the threshold.

Abstract translation: 描述了有效的技术来延长具有有限写入耐力的存储器的可用寿命。 高速缓存的磨损均衡技术解决了高速缓存线上的不平衡写入流量，这导致严重写入的高速缓存行比缓存中的其他行失败得快。 每个写入操作一个计数器递增到一个缓存数组。 受当前写入操作影响的一行导致计数器达到阈值的行从缓存中消除而不是将数据写入受影响的行。 可以根据操作程序动态调整阈值。 由于计数器达到阈值，因此停止对当前替换策略指针的更新。

公开(公告)号：US09911485B2

公开(公告)日：2018-03-06

申请号：US14244173

申请日：2014-04-03

Applicant: QUALCOMM Incorporated

Inventor： Deepti Vijayalakshmi Sriramagiri ,  Jung Pill Kim ,  Jungwon Suh ,  Xiangyu Dong

IPC: G06F12/00 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/406 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40626 ,  G11C2211/406

Abstract: A method includes sending a first signal from a memory device to a memory controller. The first signal indicates to the memory controller that particular memory cells of the memory device are to be refreshed by the memory device.

公开(公告)号：US09431129B2

公开(公告)日：2016-08-30

申请号：US14266326

申请日：2014-04-30

Applicant: QUALCOMM Incorporated

Inventor： Jung Pill Kim ,  Taehyun Kim ,  Sungryul Kim ,  Xiangyu Dong

IPC: G11C29/02 ,  G11C29/30 ,  G11C7/10 ,  G11C16/26 ,  G11C16/30 ,  G11C14/00 ,  G06F11/10 ,  G11C29/52 ,  G11C7/06 ,  G11C7/08 ,  G11C29/04 ,  G11C11/16 ,  G11C13/00

CPC classification number: G11C29/026 ,  G06F11/106 ,  G06F11/1072 ,  G06F11/1076 ,  G11C7/06 ,  G11C7/08 ,  G11C7/1006 ,  G11C7/1072 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/004 ,  G11C14/0081 ,  G11C14/009 ,  G11C16/26 ,  G11C16/30 ,  G11C29/30 ,  G11C29/52 ,  G11C2029/0411

Abstract: A device includes a plurality of memory cells of a memory array, a sense amplifier of the memory array, and selection logic of the memory array. The sense amplifier is configured to sense at least one data value from at least one memory cell of the plurality of memory cells. The selection logic is configured to select between causing the sense amplifier to sense the at least one data value using a first sensing delay and causing the sense amplifier to sense the at least one data value using a second sensing delay. The second sensing delay is longer than the first sensing delay.

Abstract translation: 一种器件包括存储器阵列的多个存储单元，存储器阵列的读出放大器和存储器阵列的选择逻辑。 感测放大器被配置为感测来自多个存储器单元中的至少一个存储单元的至少一个数据值。 选择逻辑被配置为在使感测放大器使用第一感测延迟来感测至少一个数据值并且使得感测放大器使用第二感测延迟来感测至少一个数据值之间进行选择。 第二感测延迟比第一感测延迟更长。

公开(公告)号：US09368187B2

公开(公告)日：2016-06-14

申请号：US14149543

申请日：2014-01-07

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong ,  Jung Pill Kim

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40611 ,  G11C11/40622 ,  G11C2211/4061 ,  G11C2211/4065

Abstract: A memory refresh method includes determining positions at which to insert refresh operations of weak rows of a memory block among regularly scheduled refresh operations of normal rows of the memory block. The refresh operations occur at a substantially constant refresh rate. The positions at which to insert are based on an actual weak page address. The method also includes performing inserted refresh operations at the determined positions to coordinate distribution of the inserted refresh operations among the regularly scheduled refresh operations.

Abstract translation: 存储器刷新方法包括确定在存储器块的正常行的规则调度的刷新操作中插入存储器块的弱行的刷新操作的位置。 刷新操作以基本恒定的刷新率发生。 要插入的位置基于实际的弱页面地址。 该方法还包括在所确定的位置处执行插入的刷新操作，以协调在规则排列的刷新操作之间插入的刷新操作的分布。

公开(公告)号：US09348743B2

公开(公告)日：2016-05-24

申请号：US13772400

申请日：2013-02-21

Applicant: QUALCOMM Incorporated

Inventor： Xiangyu Dong

IPC: G06F12/08 ,  G06F12/02

CPC classification number: G06F12/0238 ,  G06F12/0246 ,  G06F12/0802 ,  G06F12/0864 ,  G06F12/0891 ,  G06F2212/7211

Abstract: A cache controller includes a first register that updates after every memory location swap operation on a number of cache sets in a cache memory and resets every N−1 memory location swap operations. N is a number of the cache sets in the cache memory. The memory controller also has a second register that updates after every N−1 memory location swap operations, and resets every (N2−N) memory location swap operations. The first and second registers track a relationship between logical locations and physical locations of the cache sets.

Abstract translation: 高速缓存控制器包括第一寄存器，其在每个存储器位置交换操作之后更新高速缓冲存储器中的多个高速缓存组并且重置每个N-1个存储器位置交换操作。 N是高速缓冲存储器中的多个缓存集合。 存储器控制器还具有在每N-1个存储器位置交换操作之后更新的第二寄存器，并且重置每个（N2-N）个存储器位置交换操作。 第一和第二寄存器跟踪高速缓存集合的逻辑位置和物理位置之间的关系。