公开(公告)号：US12118098B1

公开(公告)日：2024-10-15

申请号：US18702684

申请日：2023-12-08

Applicant: PQSECURE TECHNOLOGIES, LLC

Inventor： Abubakr Abdulgadir ,  Rami ElKhatib

IPC: G06F21/60 ,  G06F7/76

CPC classification number: G06F21/602 ,  G06F7/764

Abstract: A computer processing system configured to effectuate lower-order masking in a higher-order masked design that includes a DOM Multiplication gate of order M operably configured to receive M+1 data shares for each of a plurality of variables and operably configured to perform a lower order masking of N. As used herein, M is greater than N, by disabling at least one cross-domain computation of the M+1 data shares between N+1 data shares and M−N data shares. To that end, the system and method of effectuating lower-ordered masking in a higher-order masked design beneficially by being operable to disable cross-domain computations to perform the lower-order masked operations.

公开(公告)号：US20240272873A1

公开(公告)日：2024-08-15

申请号：US18569800

申请日：2022-06-23

Applicant: GIESECKE+DEVRIENT EPAYMENTS GMBH

Inventor： Lars HOFFMANN

IPC: G06F7/76

CPC classification number: G06F7/764 ,  G06F2207/7233

Abstract: A method is provided for re-masking from a Boolean mask to an arithmetic mask with a modulus (2m*p), in which m is an integer greater than or equal to zero, and p has at least one prime divisor unequal to 2, so that a carry is generated. The carry is masked or balanced to protect it against intrusion attacks.

公开(公告)号：US20230344638A1

公开(公告)日：2023-10-26

申请号：US18030219

申请日：2020-10-06

Applicant: NEC Corporation

Inventor： Hikaru TSUCHIDA

IPC: H04L9/32 ,  H04L9/08 ,  G06F7/76

CPC classification number: H04L9/3236 ,  H04L9/0869 ,  G06F7/764

Abstract: A secure computation system comprises at least five secure computation server apparatuses connected to each other via a network and performs secure computation on a value stored while being secret-shared, and each of the secure computation server apparatuses has a comparative verification part that compares values, which should be the same, received from at least three secure computation server apparatuses and that accepts a received value identical to at least another received value as a correct value.

公开(公告)号：US20230195417A1

公开(公告)日：2023-06-22

申请号：US17559811

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Mrinmay Dutta ,  Simon Rubanovich ,  Amit Gradstein ,  Zeev Sperber

IPC: G06F7/507 ,  G06F7/76 ,  G06F7/505 ,  G06F7/501

CPC classification number: G06F7/507 ,  G06F7/501 ,  G06F7/764 ,  G06F7/5057

Abstract: One embodiment provides a processor comprising at least one of a first mask to receive a first input operand and a second input operand and to generate a selected portion of an AND of a sum of the first input operand and the second input operand using an AND chain of the first mask in parallel with generation of the sum by an adder; and a second mask to receive the first input operand and the second input operand and to generate the selected portion of an OR of the sum using an OR chain of the second mask in parallel with generation of the sum.

公开(公告)号：US20170052783A1

公开(公告)日：2017-02-23

申请号：US15346531

申请日：2016-11-08

Applicant: Intel Corporation

Inventor： MIKHAIL PLOTNIKOV ,  ANDREY NARAIKIN ,  ELMOUSTAPHA OULD-AHMED-VALL ,  ROBERT VALENTINE ,  BRET L. TOLL ,  JESUS CORBAL

IPC: G06F9/30

CPC classification number: G06F9/3013 ,  G06F7/764 ,  G06F9/3001 ,  G06F9/30014 ,  G06F9/30018 ,  G06F9/30029 ,  G06F9/30036

Abstract: A method is described that includes reading a first read mask from a first register. The method also includes reading a first vector operand from a second register or memory location. The method also includes applying the read mask against the first vector operand to produce a set of elements for operation. The method also includes performing an operation of the set elements. The method also includes creating an output vector by producing multiple instances of the operation's result. The method also includes reading a first write mask from a third register, the first write mask being different than the first read mask. The method also includes applying the write mask against the output vector to create a resultant vector. The method also includes writing the resultant vector to a destination register.

Abstract translation: 描述了一种包括从第一寄存器读取第一读取掩码的方法。 该方法还包括从第二寄存器或存储器位置读取第一向量操作数。 该方法还包括对第一向量操作数应用读取掩码以产生用于操作的一组元素。 该方法还包括执行设定元件的操作。 该方法还包括通过产生操作结果的多个实例来创建输出向量。 该方法还包括从第三寄存器读取第一写掩码，第一写掩码不同于第一读掩码。 该方法还包括针对输出向量应用写掩码以产生合成矢量。 该方法还包括将结果矢量写入目的地寄存器。

公开(公告)号：US20110270837A1

公开(公告)日：2011-11-03

申请号：US12814573

申请日：2010-06-14

Applicant: K. Antony Arokia Durai Raj ,  B. Kanagasabapathi

Inventor： K. Antony Arokia Durai Raj ,  B. Kanagasabapathi

IPC: G06F17/30 ,  G06F15/16

CPC classification number: G06F21/6227 ,  G06F7/764 ,  G06F7/768 ,  G06F21/6245 ,  G06F21/6254 ,  H04L9/0894

Abstract: A system and method for logically masking data by implementing masking algorithms is provided. The method includes receiving one or more inputs from user regarding type of data masking to be implemented depending on type of data entry. Data entries include alphabetical data, data comprising unique codes, data comprising dates and numerical data. Based on inputs received, the data entries are classified and appropriate masking algorithms are executed. For masking numerical data entries, the data entries are first grouped using clustering algorithms and are then shuffled using shuffling algorithms. For low level of data masking selected by a user, numerical data entries are shuffled within groups and for high level of data masking selected by a user, numerical data entries are shuffled across groups.

Abstract translation: 提供了一种通过实现屏蔽算法逻辑地屏蔽数据的系统和方法。 该方法包括根据数据输入的类型从用户接收关于要实现的数据掩蔽类型的一个或多个输入。 数据条目包括字母数据，包括唯一代码的数据，包括日期和数字数据的数据。 根据接收到的输入，对数据条目进行分类，并执行适当的屏蔽算法。 为了掩蔽数字数据条目，首先使用聚类算法分组数据条目，然后使用洗牌算法进行混洗。 对于用户选择的低级别的数据屏蔽，数字数据条目在组内进行混洗，并且对于用户选择的高级数据屏蔽，数字数据条目将在组间进行混洗。

公开(公告)号：US08050402B2

公开(公告)日：2011-11-01

申请号：US11791981

申请日：2004-12-01

Applicant: Jovan Golic

Inventor： Jovan Golic

IPC: G06F7/00

CPC classification number: G06F7/764 ,  G06F2207/7233 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/08 ,  H04L2209/12

Abstract: A method for secure conversion between two different random markings used for cryptographic functions, converts a first binary data word, masked by a binary mask word according to a first masking process, into a corresponding second binary data word, masked by said binary mask word according to a second masking process, the first and second binary data words and the binary mask word including corresponding pluralities of bits, wherein each of the pluralities of the bits includes a least significant bit, a first bit, and at least one i-th bit i≧2.

Abstract translation: 一种用于加密功能的两个不同随机标记之间的安全转换的方法，将根据第一掩蔽处理的二进制掩码字掩蔽的第一二进制数据字转换成相应的第二二进制数据字， 到第二掩蔽处理，第一和第二二进制数据字和二进制掩码字包括相应的多个位，其中多个位中的每一个包括最低有效位，第一位和至少一个第i位 i≥2。

公开(公告)号：US07949697B2

公开(公告)日：2011-05-24

申请号：US11882356

申请日：2007-08-01

Applicant: Kenichi Handa

Inventor： Kenichi Handa

IPC: G06F15/00

CPC classification number: G06F7/764

Abstract: A bit field operation circuit has a first shift unit, a mask shift amount control circuit, a second shift unit, a logic operation unit, and a selection unit. The first shift unit outputs a first intermediate data based on a first control signal. The mask shift amount control circuit outputs a mask shift control signal in accordance with a mask shift amount. The second shift unit outputs a second intermediate data based on a mask shift control signal. The third shift unit outputs a third intermediate data based on the first control signal. The logic operation unit performs logical operation of the second intermediate data and the third intermediate data, and outputs a mask selection data. The selection unit selects either one of the first intermediate data or the second input data based on the mask selection data to output as output data.

Abstract translation: 位场运算电路具有第一移位单元，掩码移位量控制电路，第二移位单元，逻辑运算单元和选择单元。 第一移位单元基于第一控制信号输出第一中间数据。 掩模偏移量控制电路根据掩模偏移量输出掩模移位控制信号。 第二移位单元基于掩码移位控制信号输出第二中间数据。 第三移位单元基于第一控制信号输出第三中间数据。 逻辑运算单元执行第二中间数据和第三中间数据的逻辑运算，并输出掩模选择数据。 选择单元基于掩模选择数据选择第一中间数据或第二输入数据中的任一个作为输出数据输出。

公开(公告)号：US20100318773A1

公开(公告)日：2010-12-16

申请号：US12482618

申请日：2009-06-11

Applicant: Terry D. Greyzck ,  William F. Long ,  Peter M. Klausler ,  Matthew F. Taylor

Inventor： Terry D. Greyzck ,  William F. Long ,  Peter M. Klausler ,  Matthew F. Taylor

IPC: G06F9/305 ,  G06F9/30

CPC classification number: G06F9/30018 ,  G06F7/02 ,  G06F7/764 ,  G06F9/30021 ,  G06F9/30036

Abstract: A computer system is operable to identify index elements in a vector index array that cannot be processed in parallel by calculating a complement modified bit matrix compare function between a first matrix filled with elements from the vector index array and a second matrix filled with the same elements from the vector index array.

Abstract translation: 计算机系统可操作以通过计算填充有来自向量索引阵列的元素的第一矩阵和填充有相同元素的第二矩阵之间的补码修改位矩阵比较函数来识别不能并行处理的向量索引数组中的索引元素 从矢量索引数组。

公开(公告)号：US20080191736A1

公开(公告)日：2008-08-14

申请号：US12050897

申请日：2008-03-18

Applicant: Jason Redgrave ,  Teju Khubchandani

Inventor： Jason Redgrave ,  Teju Khubchandani

IPC: H03K19/173

CPC classification number: H03K19/17776 ,  G06F7/32 ,  G06F7/764 ,  H03K19/17736 ,  H03K19/17752 ,  H03K19/17756 ,  H03K19/17764

Abstract: Some embodiments of the invention provide configurable integrated circuit (IC) that includes several configurable circuits that are conceptually in tiles. The IC also includes a first data network for passing data between the configurable circuits. The IC further includes a second packet-switch network for receiving packets of data from the outside of the configurable IC and switchably routing each packet to at least one destination tile. In some embodiments, the second packet-switch network supplies data from the tiles that the configurable circuits output in response to data packets received from outside of the configurable IC. Also, in some embodiments a particular packet that is for a particular resource in a particular tile includes a first address that identifies the particular configurable tile from the plurality of configurable tiles, and then a second address that identifies the particular resource within the particular configurable tile.

Abstract translation: 本发明的一些实施例提供了可配置集成电路（IC），其包括概念上在瓦片中的几个可配置电路。 IC还包括用于在可配置电路之间传递数据的第一数据网络。 IC还包括第二分组交换网络，用于从可配置IC的外部接收数据分组，并且可切换地将每个分组路由到至少一个目的地分块。 在一些实施例中，第二分组交换网络响应于从可配置IC的外部接收的数据分组提供可配置电路输出的瓦片中的数据。 此外，在一些实施例中，用于特定瓦片中的特定资源的特定分组包括识别来自多个可配置分块的特定可配置分块的第一地址，然后标识特定可配置分块内的特定资源的第二地址 。