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    COMPUTE ENGINE WITH TRANSPOSE CIRCUITRY
    1.
    发明公开
    COMPUTE ENGINE WITH TRANSPOSE CIRCUITRY 审中-公开

    公开(公告)号：US20240103813A1

    公开(公告)日：2024-03-28

    申请号：US17934145

    申请日：2022-09-21

    Applicant: Amazon Technologies, Inc.

    Inventor： Xiaodan Tan ,  Paul Gilbert Meyer ,  Sheng Xu ,  Ron Diamant

    IPC: G06F7/76 ,  G06F7/57 ,  G06F17/16

    CPC classification number: G06F7/768 ,  G06F7/57 ,  G06F17/16

    Abstract: An integrated circuit that combines transpose and compute operations may include a transpose circuit coupled to a set of compute channels. Each compute channel may include multiple arithmetic logic unit (ALU) circuits coupled in series. The transpose circuit is operable to receive an input tensor, transpose the input tensor, and output a transposed tensor to the set of compute channels. The set of compute channels is operable to generate outputs in parallel, with each of the outputs being generated from a corresponding vector of the transposed tensor.

    SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM
    5.
    发明申请
    SEMICONDUCTOR DEVICE AND DATA PROCESSING SYSTEM 有权
    半导体器件和数据处理系统

    公开(公告)号：US20140189166A1

    公开(公告)日：2014-07-03

    申请号：US14198414

    申请日：2014-03-05

    Applicant: Renesas Electronics Corporation

    Inventor： Goro SAKAMAKI ,  Yuri AZUMA

    IPC: G06F13/10

    CPC classification number: G09G5/39 ,  G06F7/768 ,  G06F9/4806 ,  G06F13/10 ,  G06F13/102 ,  G06F13/20 ,  G06F13/4013 ,  G06F13/4022 ,  G06F13/4063 ,  G06F13/4221 ,  G09G3/2096 ,  G09G3/36 ,  G09G3/3648 ,  G09G3/3674 ,  G09G2310/08 ,  G09G2360/10

    Abstract: The present invention is to provide a semiconductor device that can correctly switch endians on the outside even if the endian of a parallel interface is not recognized on the outside. The semiconductor device includes a switching circuit and a first register. The switching circuit switches between whether a parallel interface with the outside is to be used as a big endian or a little endian. A first register holds control data of the switching circuit. The switching circuit regards the parallel interface as the little endian when first predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register, and regards the parallel interface as the big endian when second predetermined control information, that is unchanged in the values of specific bit positions even if its high-order and low-order bit positions are transposed, is supplied to the first register. Whatever the endian setting status, the control information can be correctly inputted without being influenced by the endian setting status.

    Abstract translation: 本发明是提供一种半导体装置，即使在外部不识别到并行接口的端面，也能够正确地切换外部的端子。 半导体器件包括开关电路和第一寄存器。 开关电路是否将与外部的并行接口用作大端或小端。 第一寄存器保存开关电路的控制数据。 当第一预定控制信息（即使其高位和低位比特位置被转置时在特定比特位置的值不变）的第一预定控制信息被提供给第一寄存器时，切换电路将并行接口视为小端，并且 将并行接口视为大端，即使第二预定控制信息（即使其高位和低位比特位置被转置也在特定比特位置的值不变）被提供给第一寄存器。 无论端点设置状态如何，控制信息都可以正确输入，而不受端序设置状态的影响。

    Apparatus and method for performing rearrangement and arithmetic operations on data
    6.
    发明授权
    Apparatus and method for performing rearrangement and arithmetic operations on data 有权
    对数据执行重排和算术运算的装置和方法

    公开(公告)号：US08255446B2

    公开(公告)日：2012-08-28

    申请号：US11987323

    申请日：2007-11-29

    Applicant: Daniel Kershaw ,  Mladen Wilder ,  Dominic Hugo Symes

    Inventor： Daniel Kershaw ,  Mladen Wilder ,  Dominic Hugo Symes

    IPC: G06F7/38

    CPC classification number: G06F7/768 ,  G06F9/30032 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30112 ,  G06F9/3013 ,  G06F9/3885 ,  G06F9/3887

    Abstract: An apparatus and method are provided for performing rearrangement operations and arithmetic operations on data. The data processing apparatus has processing circuitry for performing Single Instruction Multiple Data (SIMD) processing operations and scalar processing operations, a register bank for storing data and control circuitry responsive to program instructions to control the processing circuitry to perform data processing operations. The control circuitry is arranged to responsive to a combined rearrangement arithmetic instruction to control the processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation on a plurality of data elements stored in the register bank. The rearrangement operation is configurable by a size parameter derived at least in part from the register bank. The size parameter provides an indication of a number of data elements forming a rearrangement element for the purposes of the rearrangement operation. The associated method involves controlling processing circuitry to perform a rearrangement operation and at least one SIMD arithmetic operation in response to a combined rearrangement arithmetic instruction and providing the scalar logic size parameter to configure the rearrangement operation. A computer program product is also provided comprising at least one combined rearrangement arithmetic instruction.

    Abstract translation: 提供了一种用于对数据执行重新排列操作和算术运算的装置和方法。 数据处理装置具有用于执行单指令多数据（SIMD）处理操作和标量处理操作的处理电路，响应于程序指令来存储数据和控制电路的寄存器组，以控制处理电路执行数据处理操作。 控制电路被布置为响应于组合重排算术指令来控制处理电路对存储在寄存器组中的多个数据元素执行重新排列操作和至少一个SIMD算术运算。 重新布置操作可以由至少部分地从寄存器库导出的尺寸参数来配置。 尺寸参数提供形成用于重排操作的重新排列元件的数量元素的数量的指示。 相关联的方法涉及控制处理电路以响应于组合重排算术指令执行重排操作和至少一个SIMD算术运算，并提供标量逻辑大小参数以配置重新排列操作。 还提供了包括至少一个组合重排算术指令的计算机程序产品。

    Digital electronic binary rotator and reverser
    7.
    发明授权
    Digital electronic binary rotator and reverser 有权
    数字电子二进制旋转器和反向器

    公开(公告)号：US08122074B2

    公开(公告)日：2012-02-21

    申请号：US11977729

    申请日：2007-10-25

    Applicant: James Robert Whittaker

    Inventor： James Robert Whittaker

    IPC: G06F15/00

    CPC classification number: G06F7/768 ,  G06F5/015 ,  G06F7/762

    Abstract: A binary rotator which includes an array of n cascaded 2-input multiplexer banks and received at an input 2n-bit binary data words can be used not only for rotation but also for selective reversal, without the necessity of the addition of a further multiplex bank dedicated to the reversal. This is achieved by making groups of multiplexers of at least all but one of the n banks of multiplexers separately controllable by words from control logic, rather than feeding the multiplexer banks with single control bits. The control bits are appropriately selected to provide the desired rotation-cum-reversal with just the 2n×n array of multiplexers, and can themselves be generated by appropriate logic gates.

    Abstract translation: 包括n个级联的2输入多路复用器组的阵列并且以输入的2n位二进制数据字接收的二进制旋转器不仅可用于旋转，而且可用于选择性反转，而不需要添加另外的多路复用组 致力于逆转。 这是通过使得多个复用器组中的至少所有非复用器组中的至少所有复用器的组分别由来自控制逻辑的单词控制，而不是使用单个控制位馈送多路复用器组来实现的。 适当地选择控制位以提供与2n×n多路复用器阵列的期望的旋转和反相，并且本身可以由适当的逻辑门产生。

    METHOD AND SYSTEM FOR LOGICAL DATA MASKING
    8.
    发明申请
    METHOD AND SYSTEM FOR LOGICAL DATA MASKING 有权
    用于逻辑数据显示的方法和系统

    公开(公告)号：US20110270837A1

    公开(公告)日：2011-11-03

    申请号：US12814573

    申请日：2010-06-14

    Applicant: K. Antony Arokia Durai Raj ,  B. Kanagasabapathi

    Inventor： K. Antony Arokia Durai Raj ,  B. Kanagasabapathi

    IPC: G06F17/30 ,  G06F15/16

    CPC classification number: G06F21/6227 ,  G06F7/764 ,  G06F7/768 ,  G06F21/6245 ,  G06F21/6254 ,  H04L9/0894

    Abstract: A system and method for logically masking data by implementing masking algorithms is provided. The method includes receiving one or more inputs from user regarding type of data masking to be implemented depending on type of data entry. Data entries include alphabetical data, data comprising unique codes, data comprising dates and numerical data. Based on inputs received, the data entries are classified and appropriate masking algorithms are executed. For masking numerical data entries, the data entries are first grouped using clustering algorithms and are then shuffled using shuffling algorithms. For low level of data masking selected by a user, numerical data entries are shuffled within groups and for high level of data masking selected by a user, numerical data entries are shuffled across groups.

    Abstract translation: 提供了一种通过实现屏蔽算法逻辑地屏蔽数据的系统和方法。 该方法包括根据数据输入的类型从用户接收关于要实现的数据掩蔽类型的一个或多个输入。 数据条目包括字母数据，包括唯一代码的数据，包括日期和数字数据的数据。 根据接收到的输入，对数据条目进行分类，并执行适当的屏蔽算法。 为了掩蔽数字数据条目，首先使用聚类算法分组数据条目，然后使用洗牌算法进行混洗。 对于用户选择的低级别的数据屏蔽，数字数据条目在组内进行混洗，并且对于用户选择的高级数据屏蔽，数字数据条目将在组间进行混洗。

    Fast rotator with embedded masking and method therefor
    9.
    发明申请
    Fast rotator with embedded masking and method therefor 审中-公开
    具有嵌入式掩蔽的快速旋转器及其方法

    公开(公告)号：US20070088772A1

    公开(公告)日：2007-04-19

    申请号：US11252061

    申请日：2005-10-17

    Applicant: Lincoln Nunes ,  Albert Danysh

    Inventor： Lincoln Nunes ,  Albert Danysh

    IPC: G06F7/00

    CPC classification number: G06F7/764 ,  G06F5/017 ,  G06F7/768

    Abstract: An operand rotator (100) and method of rotating an operand is disclosed. The operand rotator (100) includes a first decoder (102) with a first input to receive an operand size indicating one of a plurality of operand sizes, a second input for receiving a rotate amount signal and a control output to provide a plurality of control signals. The operand rotator (100) also includes a rotator (104) with a first input coupled to the control output of the first decoder (102), a second input to receive a data element and an output to provide rotated data. The rotator (104) is responsive to the plurality of control signals to rotate portions of the data element corresponding to one of the plurality of operand sizes by an amount corresponding to the rotate amount signal.

    Abstract translation: 公开了一种操作数旋转器（100）和旋转操作数的方法。 操作数旋转器（100）包括第一解码器（102），第一解码器（102）具有第一输入端，用于接收指示多个操作数大小之一的操作数大小，用于接收旋转量信号的第二输入端和用于提供多个控制的控制输出 信号。 操作数旋转器（100）还包括旋转器（104），其具有耦合到第一解码器（102）的控制输出的第一输入端，接收数据元件的第二输入端和提供旋转数据的输出端。 旋转器（104）响应于多个控制信号，将对应于多个操作数大小中的一个的数据元素的部分旋转与旋转量信号相对应的量。

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