公开(公告)号：US12100367B2

公开(公告)日：2024-09-24

申请号：US18227490

申请日：2023-07-28

申请人： Japan Display Inc.

发明人： Kohei Kinoshita ,  Chihiro Tanaka

IPC分类号： G09G3/36 ,  G02F1/1362 ,  G02F1/1368 ,  G06F3/041

CPC分类号： G09G3/3648 ,  G02F1/136286 ,  G02F1/1368 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2300/0426

摘要： A display device includes: pixel electrodes including a first pixel electrode and a second pixel electrode adjacent to the first pixel electrode in a first direction; switching elements including a first switching element coupled to the first pixel electrode and a second switching element coupled to the second pixel electrode; gate lines including a first gate line coupled to the first switching element and a second gate line coupled to the second switching element; a gate driver supplying a gate signal to the gate lines; and drive electrodes including a first drive electrode and a second drive electrode adjacent to the first drive electrode in the first direction. The first drive electrode overlaps the first and second pixel electrodes, and the second gate line. The second drive electrode overlaps the first gate line. The gate driver supplies the gate signal to the first and second gate lines simultaneously.

公开(公告)号：US12087245B2

公开(公告)日：2024-09-10

申请号：US18037043

申请日：2020-11-20

申请人： BOE Technology Group Co., Ltd.

发明人： Shaolei Zong ,  Jigang Sun ,  Weixin Jiang ,  Bin Wang ,  Wei Sun ,  Xin Duan ,  Shuhuan Yu ,  Kexin Hao ,  Jiaqi Fan ,  Zhaoyun Gu ,  Shaoru Zhang ,  Tieshi Wang ,  Kuanjun Peng ,  Xue Dong ,  Wei Qin ,  Weixing Liu

IPC分类号： G09G3/36 ,  G06T15/00 ,  H04N13/383

CPC分类号： G09G3/3674 ,  G06T15/00 ,  H04N13/383 ,  G09G2354/00

摘要： A display apparatus and a driving method therefor. The driving method includes: determining a gaze area and a non-gaze area of a user on a display apparatus in real time (S10); and driving the gaze area for image displaying at a first resolution, and driving the non-gaze area for image displaying at a second resolution, wherein the first resolution is higher than the second resolution. By using of the display apparatus, image resolution can be adjusted according to different areas, so as to realize high-resolution image display in a display area at which a user gazes and realize low-resolution image display in other areas, thereby reducing power consumption and achieving reasonable allocation of resources on the premise of ensuring the user experience.

公开(公告)号：US20240280869A1

公开(公告)日：2024-08-22

申请号：US18645658

申请日：2024-04-25

申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

发明人： Atsushi Umezaki

IPC分类号： G02F1/1362 ,  G02F1/133 ,  G02F1/1335 ,  G02F1/1337 ,  G02F1/1345 ,  G02F1/1368 ,  G02F1/139 ,  G09G3/34 ,  G09G3/36 ,  G11C19/28 ,  H01L21/67 ,  H01L27/06 ,  H01L27/12 ,  H01L27/15 ,  H01L29/24 ,  H01L29/786 ,  H10K50/842 ,  H10K59/121 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131 ,  H10K59/35 ,  H10K71/00 ,  H10K102/00

CPC分类号： G02F1/136286 ,  G02F1/13306 ,  G02F1/13452 ,  G02F1/136213 ,  G02F1/1368 ,  G09G3/342 ,  G09G3/3674 ,  G09G3/3677 ,  G09G3/3685 ,  G11C19/28 ,  H01L27/06 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/15 ,  H01L27/156 ,  H01L29/247 ,  H01L29/78693 ,  G02F1/133622 ,  G02F1/133753 ,  G02F1/1393 ,  G02F2202/103 ,  G09G3/3655 ,  G09G2300/0426 ,  G09G2300/0452 ,  G09G2310/024 ,  G09G2310/0286 ,  G09G2310/08 ,  G09G2320/0252 ,  G09G2330/021 ,  H01L21/67167 ,  H10K50/8426 ,  H10K59/1213 ,  H10K59/1216 ,  H10K59/123 ,  H10K59/124 ,  H10K59/131 ,  H10K59/35 ,  H10K59/351 ,  H10K59/352 ,  H10K71/00 ,  H10K2102/3023 ,  H10K2102/3026 ,  H10K2102/3031

摘要： A first transistor, a second transistor, a third transistor, a fourth transistor are provided. In the first transistor, a first terminal is electrically connected to a first wiring; a second terminal is electrically connected to a gate terminal of the second transistor; a gate terminal is electrically connected to a fifth wiring. In the second transistor, a first terminal is electrically connected to a third wiring; a second terminal is electrically connected to a sixth wiring. In the third transistor, a first terminal is electrically connected to a second wiring; a second terminal is electrically connected to the gate terminal of the second transistor; a gate terminal is electrically connected to a fourth wiring. In the fourth transistor, a first terminal is electrically connected to the second wiring; a second terminal is electrically connected to the sixth wiring; a gate terminal is connected to the fourth wiring.

公开(公告)号：US12068329B2

公开(公告)日：2024-08-20

申请号：US17560479

申请日：2021-12-23

申请人： Semiconductor Energy Laboratory Co., Ltd.

发明人： Shunpei Yamazaki ,  Hidekazu Miyairi ,  Akiharu Miyanaga ,  Kengo Akimoto ,  Kojiro Shiraishi

IPC分类号： H01L27/12 ,  H01L29/24 ,  H01L29/66 ,  H01L29/786 ,  G02F1/1333 ,  G02F1/1335 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G09G3/36 ,  H10K59/121

CPC分类号： H01L27/1225 ,  H01L29/247 ,  H01L29/66969 ,  H01L29/78618 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78693 ,  H01L29/78696 ,  G02F1/133345 ,  G02F1/133528 ,  G02F1/134336 ,  G02F1/13439 ,  G02F1/136286 ,  G02F1/1368 ,  G02F2201/123 ,  G09G3/3674 ,  G09G2310/0286 ,  H10K59/1213

摘要： An embodiment is to include an inverted staggered (bottom gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. The buffer layer having higher carrier concentration than the semiconductor layer is provided intentionally between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.

公开(公告)号：US12046175B2

公开(公告)日：2024-07-23

申请号：US17902196

申请日：2022-09-02

申请人： HKC CORPORATION LIMITED

发明人： Jianyu Cui ,  Haoxuan Zheng

IPC分类号： G09G3/20 ,  G09G3/36 ,  G02F1/1335 ,  G02F1/1345

CPC分类号： G09G3/20 ,  G09G3/2096 ,  G09G3/3674 ,  G02F1/133514 ,  G02F1/13454 ,  G09G2300/0408 ,  G09G2310/08 ,  G09G2320/0233

摘要： Disclosed are a drive circuit, an array substrate and a display panel. The first signal line is for receiving and transmitting the first reset control signal after the display of the current frame ends. First ends of the first thin film transistor and the second thin film transistor are connected to the first signal line. Second ends of the first thin film transistor and the second thin film transistor are connected to the second signal line. Third ends of the first thin film transistor and the second thin film transistor are connected to the controlled end and output end of the output module, respectively. The first thin film transistor and the second thin film transistor are for outputting the DC signal to the controlled end and the output end of the output module, respectively, upon receiving the first reset control signal, to reset the output module.

公开(公告)号：US20240233674A9

公开(公告)日：2024-07-11

申请号：US18064278

申请日：2022-12-11

申请人： Interface Technology (ChengDu) Co., Ltd. ,  Interface Optoelectronics (ShenZhen) Co., Ltd. ,  General Interface Solution Limited

发明人： De-Fu CHEN ,  Po Lun CHEN ,  Chun-Ta CHEN ,  Ta-Jen HUANG ,  Po-Tsun LIU ,  Guang-Ting ZHENG ,  Ting-Yi YI

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2330/021

摘要： The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

公开(公告)号：US12033595B2

公开(公告)日：2024-07-09

申请号：US17193662

申请日：2021-03-05

申请人： SILICON WORKS CO., LTD.

发明人： Yong Hee Kim ,  Jung Eun Baek ,  Jin Woo Park ,  Ji Won Lee ,  Do Seok Kim ,  Young Gi Kim

IPC分类号： G09G3/36

CPC分类号： G09G3/3607 ,  G09G3/3648 ,  G09G3/3674 ,  G09G3/3685 ,  G09G2300/043 ,  G09G2300/0443 ,  G09G2320/0233 ,  G09G2320/0242 ,  G09G2320/0252

摘要： An embodiment is able to improve the pure-color brightness ratio by compensating for image data of a current pixel on the basis of a result of comparing image data of a current pixel with image data of a previous pixel.

公开(公告)号：US20240135897A1

公开(公告)日：2024-04-25

申请号：US18064278

申请日：2022-12-11

申请人： Interface Technology (ChengDu) Co., Ltd. ,  Interface Optoelectronics (ShenZhen) Co., Ltd. ,  Interface Optoelectronics (Wuxi) Co., Ltd. ,  General Interface Solution Limited

发明人： De-Fu CHEN ,  Po Lun CHEN ,  Chun-Ta CHEN ,  Ta-Jen HUANG ,  Po-Tsun LIU ,  Guang-Ting ZHENG ,  Ting-Yi YI

IPC分类号： G09G3/36

CPC分类号： G09G3/3674 ,  G09G2310/08 ,  G09G2320/0214 ,  G09G2330/021

摘要： The present disclosure provides a scan driving circuit, which includes a pull-up output charging circuit, a pull-down discharge circuit, a pre-charge circuit, an anti-noise start-up circuit and an anti-noise pull-down discharge circuit. The pull-up output charging circuit is electrically connected to an output terminal, and the pull-down discharge circuit is electrically connected to the output terminal. The pre-charge circuit is electrically connected to the pull-up output charging circuit and the pull-down discharge circuit through a driving node. The anti-noise start-up circuit is electrically connected to the pre-charge circuit. The anti-noise pull-down discharge circuit is electrically connected to the anti-noise start-up circuit, and the anti-noise pull-down discharge circuit is electrically connected to the driving node.

公开(公告)号：US11961449B2

公开(公告)日：2024-04-16

申请号：US17042966

申请日：2020-08-07

申请人： Shenzhen China Star Optoelectronics Semiconductor Display Technology Co., Ltd.

发明人： Wenwu Liao ,  Mingwei Chen

IPC分类号： G09G5/00 ,  G09G3/20 ,  G09G3/36

CPC分类号： G09G3/2096 ,  G09G3/3674 ,  G09G2320/0214 ,  G09G2320/0233 ,  G09G2320/0247 ,  G09G2340/0435

摘要： A liquid crystal display (LCD) and a method for compensating current leakage of the LCD are provided. The LCD includes a thin film transistor (TFT) array having a plurality of TFTs, a gate driver configured to provide a scan signal, a source driver configured to provide a data signal, and a timing controller electrically connected to the gate driver and the source driver. The timing controller is configured to adjust a current refresh frequency according to a current frame rate and to transfer a control signal to the gate driver when the current refresh frequency is lower than a threshold frequency such that the gate driver increase a charging time of the plurality of TFTs according to the control signal.

公开(公告)号：US11815753B2

公开(公告)日：2023-11-14

申请号：US17942070

申请日：2022-09-09

申请人： SHARP KABUSHIKI KAISHA

发明人： Haruhito Yabuki

IPC分类号： G02F1/133 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/1343 ,  G02F1/137 ,  G02F1/1345 ,  G09G3/36 ,  G09G3/20

CPC分类号： G02F1/13306 ,  G02F1/137 ,  G02F1/1368 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/134309 ,  G02F1/136213 ,  G02F1/136286 ,  G09G3/2096 ,  G09G3/3674 ,  G09G3/3685 ,  G02F2202/10 ,  G09G2300/0426 ,  G09G2310/0286 ,  G09G2310/0291 ,  G09G2330/021

摘要： A liquid crystal display apparatus switches modes from a normal display mode to a stop preparation mode when a main power source voltage drops. In the display mode, a gate drive circuit sequentially applies a first gate-on pulse to gate bus lines so as to select pixel rows sequentially, and applies a second gate-on pulse to buffer capacitor scanning lines, each of which is associated with a pixel row selected by the first gate-on pulse, during a period that does not overlap a period during which the first gate-on pulse is applied, and a source drive circuit applies a display signal voltage to source bus lines. In the stop preparation mode, the gate drive circuit sequentially applies the first gate-on pulse to the gate bus lines so as to select the pixel rows sequentially, and applies the second gate-on pulse to the buffer capacitor scanning lines, each of which is associated with the pixel row selected by the first gate-on pulse, during a period that at least partially overlaps a period during which the first gate-on pulse is applied, and the source drive circuit applies 0 V to the source bus lines.