公开(公告)号：US08946710B2

公开(公告)日：2015-02-03

申请号：US13358554

申请日：2012-01-26

申请人： Kiyoshi Kato ,  Takeshi Osada

发明人： Kiyoshi Kato ,  Takeshi Osada

IPC分类号： H01L29/04 ,  H01L27/13 ,  H03K3/03 ,  H03K5/13 ,  H03K23/58 ,  H03L7/085 ,  H03L7/099 ,  H03L7/18 ,  H01L27/12 ,  H03K5/00

CPC分类号： H01L27/13 ,  H01L27/1214 ,  H01L27/1266 ,  H03K3/0315 ,  H03K5/133 ,  H03K23/582 ,  H03K2005/00039 ,  H03K2005/00202 ,  H03L7/085 ,  H03L7/0995 ,  H03L7/18

摘要： A semiconductor device with high function, multifunction and high added value. The semiconductor device includes a PLL circuit that is provided over a substrate and outputs a signal with a correct frequency. By providing such a PLL circuit over the substrate, a semiconductor device with high function, multifunction and high added value can be achieved.

摘要翻译： 具有功能高，功能多，附加值高的半导体器件。 半导体器件包括提供在衬底上并且输出具有正确频率的信号的PLL电路。 通过在衬底上设置这样的PLL电路，可以实现具有高功能，多功能和高附加值的半导体器件。

公开(公告)号：US08593179B2

公开(公告)日：2013-11-26

申请号：US13241304

申请日：2011-09-23

申请人： Takashi Tomita

发明人： Takashi Tomita

IPC分类号： H03K19/20

CPC分类号： H03H11/265 ,  H03K5/131 ,  H03K2005/00039

摘要： An inverter of a delay circuit in a semiconductor integrated device that has a high resistance to an electrostatic discharge. The delay circuit includes at least one inverter. Each inverter has high and low potential parts. The low potential part includes a pair of FETs. A source terminal of one FET is connected to a drain terminal of the other FET at a first common node. The high potential part includes another pair of FETs, with a source terminal of one FET being connected to a drain terminal of the other FET at a second common node. A power supply potential is applied to the first common node when the inverter output becomes a high potential. A ground potential is applied to the second common node when the inverter output becomes a low potential.

摘要翻译： 在半导体集成器件中的延迟电路的反相器具有高静电放电性。 延迟电路包括至少一个逆变器。 每个逆变器具有高低电位部分。 低电位部分包括一对FET。 一个FET的源极端子在第一公共节点处连接到另一个FET的漏极端子。 高电位部分包括另一对FET，其中一个FET的源极端子在第二公共节点处连接到另一个FET的漏极端子。 当逆变器输出变为高电位时，向第一公共节点施加电源电位。 当逆变器输出变为低电位时，将地电位施加到第二公共节点。

公开(公告)号：US08076980B2

公开(公告)日：2011-12-13

申请号：US12689233

申请日：2010-01-19

申请人： Yi-Heng Liu

发明人： Yi-Heng Liu

IPC分类号： H03K3/03 ,  H03B5/04

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K2005/00039 ,  H03K2005/00045 ,  H03K2005/00143 ,  H03K2005/00195

摘要： A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k≧1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.

摘要翻译： 温度补偿环形振荡器包括控制信号发生器和压控振荡器。 控制信号发生器被配置为产生至少一个控制信号，并且包括至少一个第一电阻器和第二电阻器。 第一电阻器的第一温度系数为负，第二电阻器的第二温度系数为正。 压控振荡器接收控制信号，输出振荡信号，并具有（2k + 1）级联逆变器单元，其中k≥1。 每个逆变器单元包括第一晶体管，第二晶体管和反相器。 第一晶体管具有耦合到第一电源电压的漏极和用于接收控制信号的栅极。 第二晶体管具有用于接收第二电源电压的源极和用于接收控制信号的栅极。 反相器耦合在第一和第二晶体管之间。

公开(公告)号：US20110175684A1

公开(公告)日：2011-07-21

申请号：US12689233

申请日：2010-01-19

申请人： Yi-Heng Liu

发明人： Yi-Heng Liu

IPC分类号： H03B5/04

CPC分类号： H03K3/0315 ,  H03K3/011 ,  H03K2005/00039 ,  H03K2005/00045 ,  H03K2005/00143 ,  H03K2005/00195

摘要： A temperature-compensated ring oscillator includes a control signal generator and a voltage controlled oscillator. The control signal generator is configured to generate at least one control signal, and includes at least one first resistor and second resistor. A first temperature coefficient of the first resistor is negative, and a second temperature coefficient of the second resistor is positive. The voltage controlled oscillator receives the control signal, outputs an oscillation signal, and has (2k+1) cascaded inverter units, where k≦1. Each of the inverter units includes a first transistor, a second transistor and an inverter. The first transistor has a drain coupled to a first supply voltage and a gate to receive the control signal. The second transistor has a source to receive a second supply voltage and a gate to receive the control signal. The inverter is coupled between the first and the second transistors.

摘要翻译： 温度补偿环形振荡器包括控制信号发生器和压控振荡器。 控制信号发生器被配置为产生至少一个控制信号，并且包括至少一个第一电阻器和第二电阻器。 第一电阻器的第一温度系数为负，第二电阻器的第二温度系数为正。 压控振荡器接收控制信号，输出振荡信号，并具有（2k + 1）级联逆变器单元，其中k＆nlE; 1。 每个逆变器单元包括第一晶体管，第二晶体管和反相器。 第一晶体管具有耦合到第一电源电压的漏极和用于接收控制信号的栅极。 第二晶体管具有用于接收第二电源电压的源极和用于接收控制信号的栅极。 反相器耦合在第一和第二晶体管之间。

公开(公告)号：US07936225B2

公开(公告)日：2011-05-03

申请号：US12333665

申请日：2008-12-12

申请人： Takeshi Osada

发明人： Takeshi Osada

IPC分类号： H03K3/03

CPC分类号： H03L7/0995 ,  H03K5/133 ,  H03K2005/00039 ,  H03K2005/0013 ,  H03L7/18

摘要： A VCO circuit includes: a control portion to which a first voltage is inputted and from which a second voltage corresponding to the first voltage is outputted; a current source portion to which the second voltage is inputted and from which a current corresponding to the second voltage is outputted; and an oscillator circuit to which the current is inputted and from which a signal with a frequency in accordance with the current is outputted. The control portion includes an adjusting circuit which changes the second voltage in conjunction with fluctuation of a power supply voltage. Accordingly, fluctuation of the frequency Fo of an output signal of the VCO circuit can be suppressed even when the power supply voltage of the VCO circuit fluctuates.

摘要翻译： VCO电路包括：输入第一电压并从其输出与第一电压对应的第二电压的控制部分; 输入第二电压的电流源部，并输出与第二电压对应的电流; 以及输入电流的振荡器电路，并且从该振荡器电路输出具有与电流相关的频率的信号。 控制部分包括调整电路，其随着电源电压的波动而改变第二电压。 因此，即使当VCO电路的电源电压波动时也可以抑制VCO电路的输出信号的频率Fo的波动。

公开(公告)号：US20100253405A1

公开(公告)日：2010-10-07

申请号：US12417497

申请日：2009-04-02

申请人： Xiaohong Quan ,  Tongyu Song ,  Lennart Mathe ,  Dinesh J. Alladi

发明人： Xiaohong Quan ,  Tongyu Song ,  Lennart Mathe ,  Dinesh J. Alladi

IPC分类号： H03L7/06

CPC分类号： H03L7/0812 ,  H03K5/1515 ,  H03K5/1565 ,  H03K2005/00039 ,  H03K2005/00097 ,  H03K2005/00286 ,  H03M1/12

摘要： Techniques for generating precise non-overlap time and clock phase delay time across a desired frequency range are provided. In one configuration, a device includes a non-overlapping clock generation circuit which comprises a delay lock loop (DLL) circuit that in turn generates a control voltage to a clock generator circuit coupled thereto. The control voltage operates to maintain precise timing relationship of non-overlapping delayed clock signals generated by the clock generator circuit. In one aspect, the DLL circuit receives an input clock with a known duty cycle and derives an output control voltage to fix the unit delay to a certain portion of the input clock cycle. In a further aspect, the clock generator circuit includes a plurality of voltage-controlled delay cells coupled to the DLL circuit to generate a first set of clock signals and a second set of clock signals delayed from the first set of clock signals by a non-overlapping time (tnlp) that is independent of manufacturing process variations.

摘要翻译： 提供了用于在所需频率范围内产生精确的非重叠时间和时钟相位延迟时间的技术。 在一种配置中，设备包括不重叠的时钟产生电路，其包括延迟锁定环（DLL）电路，该延迟锁定环路（DLL）电路又向与其耦合的时钟发生器电路产生控制电压。 控制电压操作以保持由时钟发生器电路产生的不重叠的延迟时钟信号的精确定时关系。 在一个方面，DLL电路接收具有已知占空比的输入时钟，并且导出输出控制电压以将单位延迟固定到输入时钟周期的某一部分。 在另一方面，时钟发生器电路包括耦合到DLL电路的多个电压控制延迟单元，以产生第一组时钟信号和从第一组时钟信号延迟的第二组时钟信号， 重叠时间（tnlp），与制造过程变化无关。

公开(公告)号：US07733150B2

公开(公告)日：2010-06-08

申请号：US12192385

申请日：2008-08-15

申请人： Chiaki Takano

发明人： Chiaki Takano

IPC分类号： G06F1/04

CPC分类号： H03K5/13 ,  H03K5/1506 ,  H03K2005/00039 ,  H03K2005/0013

摘要： Methods and apparatus for distributing a clock signal to a digital circuit provide for: producing a clock signal; and delaying, advanced, or leaving the clock signal unchanged to produce an output clock signal as a function of a control signal, wherein an amount of delay or advancement between the clock signal and the output clock signal (phase difference) is a function of time variant changes in a magnitude of a power supply voltage to the digital circuit.

摘要翻译： 用于将时钟信号分配给数字电路的方法和装置提供：产生时钟信号; 并且延迟，提前或者使时钟信号不变以产生作为控制信号的函数的输出时钟信号，其中时钟信号和输出时钟信号之间的延迟或提前量（相位差）是时间的函数 变化到数字电路的电源电压的大小。

公开(公告)号：US07592842B2

公开(公告)日：2009-09-22

申请号：US12002988

申请日：2007-12-18

申请人： Robert Paul Masleid

发明人： Robert Paul Masleid

IPC分类号： H03H11/26 ,  H03K19/094

CPC分类号： H03K5/131 ,  H03K2005/00039

摘要： A stacked inverter delay chain. The stacked inverter delay chain includes a plurality of stacked inverter delay elements. A switch circuit is included and is coupled to the stacked inverter delay elements and configured to select at least one of the plurality of stacked inverter delay elements to create a delay signal path. The delay signal path has an amount of delay in accordance with a number of stacked inverter delay elements comprising the delay signal path. An input is coupled to a first stacked inverter delay element of the delay signal path to receive an input signal and an output is coupled to the switch circuit and is coupled to the delay signal path to receive a delayed version of the input signal after propagating through the delay signal path.

摘要翻译： 堆叠逆变器延迟链。 层叠逆变器延迟链包括多个堆叠的反相器延迟元件。 包括开关电路并且耦合到堆叠的反相器延迟元件并且被配置为选择多个堆叠的反相器延迟元件中的至少一个以产生延迟信号路径。 延迟信号路径具有根据包括延迟信号路径的层叠逆变器延迟元件的数量的延迟量。 输入耦合到延迟信号路径的第一堆叠反相器延迟元件以接收输入信号，并且输出耦合到开关电路，并且耦合到延迟信号路径，以在传播之后接收输入信号的延迟版本 延迟信号路径。

公开(公告)号：US07498882B2

公开(公告)日：2009-03-03

申请号：US11407371

申请日：2006-04-18

申请人： William J. Dally ,  John W. Poulton

发明人： William J. Dally ,  John W. Poulton

IPC分类号： H03G3/10

CPC分类号： H03G3/3036 ,  H03G3/3052 ,  H03K2005/00039

摘要： An integrated circuit device includes a variable-gain amplifier, memory circuit and gain control update circuit. The variable-gain amplifier generates an amplified signal having an amplitude according to a gain control value that is stored, at least during a first interval, within the memory circuit. The update circuit generates an updated gain control value based on the amplified signal during the first interval, and outputs the updated gain control value to the memory circuit to be stored therein at a conclusion of the first interval.

摘要翻译： 集成电路装置包括可变增益放大器，存储电路和增益控制更新电路。 可变增益放大器至少在第一间隔期间内在存储器电路内产生具有根据增益控制值的幅度的放大信号。 更新电路基于第一间隔期间的放大信号产生更新的增益控制值，并且在第一间隔的结论处将更新的增益控制值输出到要存储在其中的存储器电路。

公开(公告)号：US07432752B1

公开(公告)日：2008-10-07

申请号：US11739594

申请日：2007-04-24

申请人： Bumha Lee ,  Sing W. Chin

发明人： Bumha Lee ,  Sing W. Chin

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K5/06 ,  H03K5/133 ,  H03K2005/00032 ,  H03K2005/00039

摘要： A duty cycle stabilizer circuit (50) receiving an input clock signal and generating an output clock signal having a first duty cycle includes a leading edge pulse generator (52) and a pulse width extender circuit (54). The pulse generator generates a first clock pulse (V1) having a leading edge triggered by the leading edge of the input clock signal and a first pulse width. The pulse width extender circuit generates a second clock pulse (V2) having a leading edge triggered by the leading edge of the first clock pulse and a pulse width being stretched to the desired duty cycle. The duty cycle stabilizer further includes a buffer (64) providing the output clock signal having the first duty cycle, a charge pump (56) receiving the output clock signal directly and a differential amplifier (62) generating an output signal for controlling the pulse width of the first and second clock pulses.

摘要翻译： 接收输入时钟信号并产生具有第一占空比的输出时钟信号的占空比稳定器电路（50）包括前沿脉冲发生器（52）和脉冲宽度延长器电路（54）。 脉冲发生器产生具有由输入时钟信号的前沿触发的前沿和第一脉冲宽度的第一时钟脉冲（V SUB 1）。 脉冲宽度延长电路产生具有由第一时钟脉冲的前沿触发的前沿的脉冲宽度被延伸至期望的占空比的第二时钟脉冲（V SUB 2）。 占空比稳定器还包括提供具有第一占空比的输出时钟信号的缓冲器（64），直接接收输出时钟信号的电荷泵（56）和产生用于控制脉冲宽度的输出信号的差分放大器 的第一和第二时钟脉冲。