公开(公告)号：US10523194B2

公开(公告)日：2019-12-31

申请号：US15717276

申请日：2017-09-27

申请人： Apple Inc.

发明人： Jaroslav Raszka ,  Amrinder S. Barn ,  Victor Zyuban ,  Shingo Suzuki ,  Ajay Kumar Bhatia ,  Mohamed H. Abu-Rahma ,  Shahzad Nazar ,  Greg M. Hess

IPC分类号： H03K17/16 ,  H03K17/14 ,  H03K19/00 ,  H03K19/003

摘要： A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.

公开(公告)号：US09311967B2

公开(公告)日：2016-04-12

申请号：US14291582

申请日：2014-05-30

申请人： Apple Inc.

发明人： Ajay Kumar Bhatia ,  Anshul Y. Mehta ,  Amrinder S. Barn ,  Greg M. Hess

IPC分类号： G11C5/14 ,  G11C7/00 ,  G11C29/02 ,  G11C29/52 ,  G11C29/04 ,  G11C29/44

CPC分类号： G11C5/147 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2029/4402

摘要： A system, a memory device and a method are contemplated in which the apparatus may include a plurality of memory cells, a plurality of voltage reduction circuits, and control circuitry. The plurality of voltage reduction circuits may be configured to reduce a voltage level of a power supply coupled to the plurality of memory cells. The control circuitry may be configured to select one of the voltage reduction circuits based on one or more operating parameters. The control circuitry may be further configured to activate the selected voltage reduction circuit upon receiving a write command directed towards the memory cells. The control circuitry may be further configured to execute the write command. Upon completion of the write command, the control circuitry may be further configured to de-activate the selected one of the voltage reduction circuits.

摘要翻译： 可以想到一种系统，存储器件和方法，其中该装置可以包括多个存储器单元，多个电压降低电路和控制电路。 多个电压降低电路可以被配置为降低耦合到多个存储器单元的电源的电压电平。 控制电路可以被配置为基于一个或多个操作参数来选择一个电压降低电路。 控制电路还可以被配置为在接收到针对存储器单元的写入命令时激活所选择的电压降低电路。 控制电路还可以被配置为执行写命令。 在完成写入命令之后，控制电路还可以被配置为去激活所选择的一个电压降低电路。

公开(公告)号：US20140219009A1

公开(公告)日：2014-08-07

申请号：US13761646

申请日：2013-02-07

申请人： APPLE INC.

发明人： Daniel C Chow ,  Hang Huang ,  Ajay Kumar Bhatia ,  Steven C Sullivan

IPC分类号： G11C7/10 ,  G11C11/412

CPC分类号： G11C7/1096 ,  G11C5/145 ,  G11C11/419

摘要： Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

摘要翻译： 公开了可以在写入期间允许数据线的负升压的存储器的实施例。 存储器件可以包括数据输入电路，地址解码电路和多个子阵列。 每个子阵列可以包括多个列，写入选择电路，第一写入驱动器电路，第二写入驱动器电路和升压电路。 每个列可以包括多个数据存储单元。 写选择电路可以选择多列的列。 每个写入驱动器电路可以被配置为将所选列的数据线放电到公共节点中。 升压电路可以被配置为将公共节点初始化为第一电压电平并将公共节点耦合到第二电压电平，其中第二电压电平低于第一电压电平。

公开(公告)号：US10187061B1

公开(公告)日：2019-01-22

申请号：US15625642

申请日：2017-06-16

申请人： Apple Inc.

发明人： Vivekanandan Venugopal ,  Ajay Kumar Bhatia ,  Michael R. Seningen

IPC分类号： H03K19/0185 ,  H03K19/00 ,  H03K5/08 ,  H03K3/037

摘要： An apparatus and method for operating a level shifter circuit that receives an input signal of interderminate voltage level is disclosed. The level shifter circuit may receive the input signal from a circuit block coupled to a first power supply signal, and generate an output signal using a second power supply signal, different than the first power supply signal. The level shifter circuit may clamp a storage node included in the level shifter circuit, and isolated at least one circuit path included in the level shifter circuit in response to a determination that an isolation signal has been enabled.

公开(公告)号：US20170366170A1

公开(公告)日：2017-12-21

申请号：US15355109

申请日：2016-11-18

申请人： Apple Inc.

发明人： Zhao Wang ,  Sheela R. Shreedharan ,  Ajay Kumar Bhatia ,  Michael R. Seningen

IPC分类号： H03K3/012 ,  H03K3/3562

CPC分类号： H03K3/012 ,  H03K3/35625

摘要： An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.

公开(公告)号：US08964490B2

公开(公告)日：2015-02-24

申请号：US13761646

申请日：2013-02-07

申请人： Apple Inc.

发明人： Daniel C Chow ,  Hang Huang ,  Ajay Kumar Bhatia ,  Steven C Sullivan

IPC分类号： G11C7/12 ,  G11C7/10 ,  G11C5/14 ,  G11C11/419

CPC分类号： G11C7/1096 ,  G11C5/145 ,  G11C11/419

摘要： Embodiments of a memory are disclosed that may allow for a negative boost of data lines during a write. The memory device may include a data input circuit, an address decode circuit and a plurality of sub-arrays. Each of the sub-arrays may include a plurality of columns, a write selection circuit, a first write driver circuit, a second write driver circuit, and a boost circuit. Each of the columns may include a plurality of data storage cells. The write selection circuit may select a column of the plurality of columns. Each of the write driver circuits may be configured to discharge a data line of a selected column into a common node. The boost circuit may be configured to initialize the common node to the first voltage level and couple the common node to a second voltage level, where the second voltage level is lower than the first voltage level.

摘要翻译： 公开了可以在写入期间允许数据线的负升压的存储器的实施例。 存储器件可以包括数据输入电路，地址解码电路和多个子阵列。 每个子阵列可以包括多个列，写入选择电路，第一写入驱动器电路，第二写入驱动器电路和升压电路。 每个列可以包括多个数据存储单元。 写选择电路可以选择多列的列。 写入驱动器电路中的每一个可以被配置为将所选列的数据线放电到公共节点中。 升压电路可以被配置为将公共节点初始化为第一电压电平并将公共节点耦合到第二电压电平，其中第二电压电平低于第一电压电平。

公开(公告)号：US20140380068A1

公开(公告)日：2014-12-25

申请号：US13921475

申请日：2013-06-19

申请人： Apple Inc.

发明人： Bo Tang ,  Ajay Kumar Bhatia

IPC分类号： G06F1/32 ,  G05F1/46

CPC分类号： G06F1/3275 ,  G05F1/468 ,  G06F1/26 ,  G06F1/32

摘要： A system including control logic, a voltage reference, a sense amplifier, and a voltage supply circuit is presented. The sense amplifier may be configured to detect a current state of the voltage supply circuit output compared to the reference voltage. The voltage supply circuit may be configured to capture and preserve the current state to be used as a previous state. The voltage regulator may be configured to compare the current state to one or more previous states and adjust the voltage regulator output based on the comparison. Control logic may be configured to enable the voltage reference output in response to a signal. Control logic may be configured to enable the sense amplifier at a time after the voltage reference is stable. Control logic may be configured to disable the voltage reference output in response to the sense amplifier generating an output.

摘要翻译： 提出了一种包括控制逻辑，电压基准，读出放大器和电压供应电路的系统。 读出放大器可被配置为检测与参考电压相比的电压供应电路输出的当前状态。 电压供给电路可以被配置为捕获并保持用作先前状态的当前状态。 电压调节器可以被配置为将当前状态与一个或多个先前状态进行比较，并且基于比较来调节稳压器输出。 控制逻辑可以被配置为响应于信号启用电压参考输出。 控制逻辑可以被配置为在电压参考稳定之后的时间使能读出放大器。 控制逻辑可以被配置为响应于感测放大器产生输出来禁用电压参考输出。

公开(公告)号：US20210167759A1

公开(公告)日：2021-06-03

申请号：US17173055

申请日：2021-02-10

申请人： Apple Inc.

发明人： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC分类号： H03K3/037 ,  H03K19/096 ,  H03K3/64

摘要： A system and method for efficiently storing and driving data between pipeline stages. In various embodiments, a flip-flop circuit includes a bypass circuit, which is a tri-state inverter, and the bypass circuit receives a clock signal and a version of a data signal. When the clock signal received by the flip-flop circuit is asserted, the output of the bypass circuit is sent as the output of the flip-flop circuit. In one example, the version of the data signal received by the bypass circuit is the data signal. In another example, the version of the data signal received by the bypass circuit is the output of a master latch. Although the output of the master latch is pre-charged, when the clock is asserted, each of a late arriving rising and falling data transition are included in the critical path of the flip-flop circuit.

公开(公告)号：US20190235602A1

公开(公告)日：2019-08-01

申请号：US16379451

申请日：2019-04-09

申请人： Apple Inc.

发明人： Vivekanandan Venugopal ,  Ajay Kumar Bhatia

IPC分类号： G06F1/3206 ,  H03K17/22 ,  G06F17/50 ,  H03K17/62

摘要： A method and apparatus for controlling a power switch are disclosed. A power switch may be coupled between a power supply signal and a virtual power supply signal coupled to a circuit block. The power switch may be configured to couple the power supply signal to the virtual power supply signal based on a first control signal, and reduce a voltage level of the virtual power supply signal to a voltage level less than a voltage level of the power supply signal based on a second control signal. The power switch may be further configured to change a current flowing from the power supply signal to the virtual power supply signal based on a third control signal.

公开(公告)号：US20190097622A1

公开(公告)日：2019-03-28

申请号：US15717276

申请日：2017-09-27

申请人： Apple Inc.

发明人： Jaroslav Raszka ,  Amrinder S. Barn ,  Victor Zyuban ,  Shingo Suzuki ,  Ajay Kumar Bhatia ,  Mohamed H. Abu-Rahma ,  Shahzad Nazar ,  Greg M. Hess

IPC分类号： H03K17/16

CPC分类号： H03K17/162 ,  H03K17/145 ,  H03K19/0016 ,  H03K19/00369 ,  H03K2217/0027 ,  H03K2217/0036

摘要： A power switch control circuit is disclosed. A sensor circuit may determine a leakage current of a power switch coupled to a power supply signal and a power terminal of a circuit block. The power switch may be configured to selectively couple or decouple the circuit block from the power supply signal using a switch control signal. The switch control circuit may, in response to receiving a request to open the power switch, determine a target voltage level that is greater than a voltage level of the power supply signal for the switch control signal using the leakage current, and transition the switch control signal from an initial voltage to the target voltage level.