知搜-全球专利检索

  1. Login
  2. Sign Up

Search Results

44 records (took 0.02 seconds)

    Data pattern based cache management
    1.
    发明授权
    Data pattern based cache management 有权

    公开(公告)号：US11755480B2

    公开(公告)日：2023-09-12

    申请号：US17929544

    申请日：2022-09-02

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen

    IPC: G06F12/08 ,  G06F12/0802

    CPC classification number: G06F12/0802 ,  G06F2212/60

    Abstract: A cache memory circuit that evicts cache lines based on which cache lines are storing background data patterns is disclosed. The cache memory circuit can store multiple cache lines and, in response to receiving a request to store a new cache line, can select a particular one of previously stored cache lines. The selection may be performed based on data patterns included in the previously stored cache lines. The cache memory circuit can also perform accesses where the internal storage arrays are not activated in response to determining data in the location specified by the requested address is background data. In systems employing virtual addresses, a translation lookaside buffer can track the location of background data in the cache memory circuit.

    Level shifting circuit with data resolution and grounded input nodes
    2.
    发明授权
    Level shifting circuit with data resolution and grounded input nodes 有权

    公开(公告)号：US10187061B1

    公开(公告)日：2019-01-22

    申请号：US15625642

    申请日：2017-06-16

    Applicant: Apple Inc.

    Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia ,  Michael R. Seningen

    IPC: H03K19/0185 ,  H03K19/00 ,  H03K5/08 ,  H03K3/037

    Abstract: An apparatus and method for operating a level shifter circuit that receives an input signal of interderminate voltage level is disclosed. The level shifter circuit may receive the input signal from a circuit block coupled to a first power supply signal, and generate an output signal using a second power supply signal, different than the first power supply signal. The level shifter circuit may clamp a storage node included in the level shifter circuit, and isolated at least one circuit path included in the level shifter circuit in response to a determination that an isolation signal has been enabled.

    REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP
    5.
    发明申请
    REDUCED POWER SET-RESET LATCH BASED FLIP-FLOP 审中-公开

    公开(公告)号：US20170366170A1

    公开(公告)日：2017-12-21

    申请号：US15355109

    申请日：2016-11-18

    Applicant: Apple Inc.

    Inventor： Zhao Wang ,  Sheela R. Shreedharan ,  Ajay Kumar Bhatia ,  Michael R. Seningen

    IPC: H03K3/012 ,  H03K3/3562

    CPC classification number: H03K3/012 ,  H03K3/35625

    Abstract: An apparatus includes a master latch circuit including a first circuit and a second circuit, and a slave latch circuit including a third circuit and a fourth circuit. The first circuit and the second circuit may be coupled to a first shared circuit node, and the third circuit and the fourth circuit may be coupled to a second shared circuit node. The master latch circuit may be configured to store a value of an input signal in response to an assertion of a clock signal. The slave latch circuit may be configured to store an output value of the master latch circuit in response to a de-assertion of the clock signal. The master latch circuit may also be configured to de-couple the first shared circuit node from a ground reference node in response to the de-assertion of the clock signal.

    ON-DIE SYSTEM FOR MONITORING AND PREDICTING PERFORMANCE
    6.
    发明申请
    ON-DIE SYSTEM FOR MONITORING AND PREDICTING PERFORMANCE 有权
    用于监测和预测性能的自适应系统

    公开(公告)号：US20160154055A1

    公开(公告)日：2016-06-02

    申请号：US14556798

    申请日：2014-12-01

    Applicant: Apple Inc.

    Inventor： Brian S. Leibowitz ,  Mohamed H. Abu-Rahma ,  Michael R. Seningen

    IPC: G01R31/28

    CPC classification number: G01R31/2896 ,  G01R31/2874 ,  G01R31/31935

    Abstract: An apparatus and method for determining performance of system is disclosed. While operating in a test mode, a plurality of test results may be received and stored in a memory. Each test result may be indicative of a performance of the system when the system is operating under a respective test condition. Also, during the test mode, a respective value of an operating parameter of a predetermined system element at each test condition. An association between each test result and a corresponding detected respective value of the operating parameter may be provided. During a normal operating mode, an operating value of the operating parameter may be determined. A performance level of the system based on a test value retrieved from memory dependent upon the operating value and the association may then be determined.

    Abstract translation: 公开了一种用于确定系统性能的装置和方法。 当在测试模式下操作时，可以接收多个测试结果并将其存储在存储器中。 当系统在相应的测试条件下操作时，每个测试结果可以指示系统的性能。 此外，在测试模式期间，在每个测试条件下的预定系统元件的操作参数的相应值。 可以提供每个测试结果与操作参数的相应检测到的相应值之间的关联。 在正常操作模式期间，可以确定操作参数的操作值。 然后可以确定基于依赖于操作值和关联的从存储器检索的测试值的系统的性能级别。

    Mode Based Skew to Reduce Scan Instantaneous Voltage Drop and Peak Currents
    7.
    发明申请
    Mode Based Skew to Reduce Scan Instantaneous Voltage Drop and Peak Currents 有权
    基于模式的倾斜以减少扫描瞬时电压降和峰值电流

    公开(公告)号：US20160061889A1

    公开(公告)日：2016-03-03

    申请号：US14468394

    申请日：2014-08-26

    Applicant: Apple Inc.

    Inventor： Asad A. Bawa ,  Benjamin A. Marrou ,  Christopher Ng ,  Michael R. Seningen ,  Mihir S. Sabnis ,  Zameeruddin Mohammed ,  Yi Zhao

    IPC: G01R31/3177

    CPC classification number: G01R31/318552 ,  G01R31/3177 ,  G01R31/318541 ,  G01R31/318563 ,  G01R31/318575

    Abstract: A method and apparatus for implementing mode based skew is disclosed. In one embodiment, an IC includes a number of different functional units each coupled to receive a respective one of a number of different clock signals. One or more of the functional circuit blocks includes at least two clock-gating circuits that are coupled to receive the clock signal provided to that functional circuit block. During a scan test, a first clock-gating circuit within a functional circuit block is configured to provide a first delay to the clock signal. A second clock-gating circuit within the functional circuit block may provide a second delay to the clock signal, the second delay being different from the first.

    Abstract translation: 公开了一种用于实现基于模式的偏斜的方法和装置。 在一个实施例中，IC包括多个不同的功能单元，每个功能单元被耦合以接收多个不同时钟信号中的相应一个。 一个或多个功能电路块包括至少两个时钟门控电路，其被耦合以接收提供给该功能电路块的时钟信号。 在扫描测试期间，功能电路块内的第一时钟选通电路被配置为向时钟信号提供第一延迟。 功能电路块内的第二时钟选通电路可以向时钟信号提供第二延迟，第二延迟与第一延迟不同。

    Memory with bit line current injection
    8.
    发明授权
    Memory with bit line current injection 有权
    内存带位线电流注入

    公开(公告)号：US09076556B2

    公开(公告)日：2015-07-07

    申请号：US14291042

    申请日：2014-05-30

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Michael E. Runas

    IPC: G11C29/00 ,  G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12

    CPC classification number: G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1204 ,  G11C2029/5002

    Abstract: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.

    Abstract translation: 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。

    MEMORY WITH BIT LINE CURRENT INJECTION
    9.
    发明申请
    MEMORY WITH BIT LINE CURRENT INJECTION 审中-公开
    记忆线路电流注入

    公开(公告)号：US20140269124A1

    公开(公告)日：2014-09-18

    申请号：US14291042

    申请日：2014-05-30

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Michael E. Runas

    IPC: G11C29/50 ,  G11C7/06

    CPC classification number: G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1204 ,  G11C2029/5002

    Abstract: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.

    Abstract translation: 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。

    Memory with redundant sense amplifier
    10.
    发明授权
    Memory with redundant sense amplifier 有权
    内存带冗余读出放大器

    公开(公告)号：US08780650B2

    公开(公告)日：2014-07-15

    申请号：US14024017

    申请日：2013-09-11

    Applicant: Apple Inc.

    Inventor： Michael R. Seningen ,  Michael E. Runas

    IPC: G11C7/22 ,  G11C7/00 ,  G11C7/02

    CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

    Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

    Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

Patent Agency Ranking