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公开(公告)号：US20250094093A1
公开(公告)日：2025-03-20
申请号：US18610974
申请日：2024-03-20
Applicant: Apple Inc.
Inventor： Eran Tamari , Brian S. Leibowitz
IPC: G06F3/06
Abstract: Techniques are disclosed relating to computing systems that use silicon photonics. In some embodiments, a computing system includes a plurality of compute die packages that include processors configured to execute program instructions that operate on data stored in a distributed memory accessible via a unified memory architecture. The computing system further includes a plurality of memory die packages configured to implement the unified memory architecture such that a given one of the memory die packages includes one or more optical interfaces configured to receive memory requests from the processors and one or more memory controllers configured to access a portion of the distributed memory in response to the received memory requests.
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公开(公告)号：US11689351B2
公开(公告)日：2023-06-27
申请号：US17482302
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
CPC classification number: H04L7/0079 , H04L7/0016 , H04L25/03878
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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公开(公告)号：US20230093114A1
公开(公告)日：2023-03-23
申请号：US17482322
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz , Shah M. Sharif
IPC: H03M1/06
Abstract: A serial data receiver circuit included in a computer system may include a front-end circuit, a sample circuit that includes multiple analog-to-digital converter circuits, and a recovery circuit. The front-end circuit may generate an equalized signal using multiple signals that encode a serial data stream of multiple data symbols. Based on a baud rate of the serial data stream, a determined number of the multiple analog-to-digital converter circuits sample, using a recovered clock signal, the equalized signal at the respective times to generate corresponding samples. The recovery circuit generates, using the samples, the recovered clock signal and recovered data symbols.
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公开(公告)号：US10924124B2
公开(公告)日：2021-02-16
申请号：US16851821
申请日：2020-04-17
Applicant: Apple Inc.
Inventor： Brian S. Leibowitz , Jared L. Zerbe , Sanjay Pant
Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
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公开(公告)号：US20200274538A1
公开(公告)日：2020-08-27
申请号：US16803861
申请日：2020-02-27
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Sanjay Pant
Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
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Patent Agency Ranking
公开(公告)号：US10581440B2
公开(公告)日：2020-03-03
申请号：US15419218
申请日：2017-01-30
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Sanjay Pant
Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
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公开(公告)号：US10230379B2
公开(公告)日：2019-03-12
申请号：US15146374
申请日：2016-05-04
Applicant: Apple Inc.
Inventor： Brian S. Leibowitz , Jared L. Zerbe , Sanjay Pant
Abstract: Techniques are disclosed relating to rapidly downshifting the output frequency of an oscillator. In some embodiments, the oscillator is configured to operate in a closed-loop mode in which negative feedback is used to maintain a particular output frequency (e.g., in a phase-locked loop (PLL)). In some embodiments, the negative feedback loop is configured to maintain the output of the oscillator at a particular frequency based on a reference clock signal and the output of the oscillator. The nature of a negative feedback loop may render rapid frequency changes difficult, e.g., because of corrections by the loop. Therefore, in some embodiments, the loop is configured to switch to an open-loop mode in which a control input to the oscillator is fixed. In some embodiments, the loop switches to open-loop mode in response to a trigger signal and control circuitry forces the oscillator to a new target frequency.
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公开(公告)号：US20160154055A1
公开(公告)日：2016-06-02
申请号：US14556798
申请日：2014-12-01
Applicant: Apple Inc.
Inventor： Brian S. Leibowitz , Mohamed H. Abu-Rahma , Michael R. Seningen
IPC: G01R31/28
CPC classification number: G01R31/2896 , G01R31/2874 , G01R31/31935
Abstract: An apparatus and method for determining performance of system is disclosed. While operating in a test mode, a plurality of test results may be received and stored in a memory. Each test result may be indicative of a performance of the system when the system is operating under a respective test condition. Also, during the test mode, a respective value of an operating parameter of a predetermined system element at each test condition. An association between each test result and a corresponding detected respective value of the operating parameter may be provided. During a normal operating mode, an operating value of the operating parameter may be determined. A performance level of the system based on a test value retrieved from memory dependent upon the operating value and the association may then be determined.
Abstract translation: 公开了一种用于确定系统性能的装置和方法。 当在测试模式下操作时，可以接收多个测试结果并将其存储在存储器中。 当系统在相应的测试条件下操作时，每个测试结果可以指示系统的性能。 此外，在测试模式期间，在每个测试条件下的预定系统元件的操作参数的相应值。 可以提供每个测试结果与操作参数的相应检测到的相应值之间的关联。 在正常操作模式期间，可以确定操作参数的操作值。 然后可以确定基于依赖于操作值和关联的从存储器检索的测试值的系统的性能级别。
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公开(公告)号：US11736111B2
公开(公告)日：2023-08-22
申请号：US17455338
申请日：2021-11-17
Applicant: Apple Inc.
Inventor： Jared L. Zerbe , Brian S. Leibowitz , Sanjay Pant
CPC classification number: H03L7/099 , H03L1/00 , H03L7/0805
Abstract: Techniques are disclosed relating to detecting supply voltage events and performing corrective actions. In some embodiments, an apparatus includes sensor circuitry and control circuitry. In some embodiments, the sensor circuitry is configured to monitor supply voltage from a power supply and detect a load release event that includes an increase in the supply voltage that meets one or more pre-determined threshold parameters. In some embodiments, the control circuitry is configured to increase clock cycle time for operations performed by circuitry powered by the supply voltage during a time interval, wherein the time interval corresponds to ringing of the supply voltage that reduces the supply voltage and results from the load release event. In some embodiments, the disclosed techniques may reduce transients in supply voltage (which may avoid equipment damage and computing errors) and may allow for reduced voltage margins (which may reduce overall power consumption).
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公开(公告)号：US20230092906A1
公开(公告)日：2023-03-23
申请号：US17482302
申请日：2021-09-22
Applicant: Apple Inc.
Inventor： Ryan D. Bartling , Jafar Savoj , Brian S. Leibowitz
Abstract: A hybrid receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. Depending on a baud rate of the serial data stream, either the digital receive circuit or the analog receiver circuit is activated to provide the desired performance and power consumption over the range of possible baud rates. The ADC-based receiver circuit may include multiple analog-to-digital converter circuits with different resolutions that can be selected for different baud rates.
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