公开(公告)号：US09076556B2

公开(公告)日：2015-07-07

申请号：US14291042

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C29/00 ,  G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12

CPC classification number: G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.

Abstract translation: 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。

公开(公告)号：US20140269124A1

公开(公告)日：2014-09-18

申请号：US14291042

申请日：2014-05-30

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C29/50 ,  G11C7/06

CPC classification number: G11C29/50 ,  G11C7/06 ,  G11C11/41 ,  G11C29/12 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may allow for the detection of weak data storage cells or may allow operation of data storage cells under conditions that may represent the effects of transistor ageing. The memory may include data storage cells, a column multiplexer, a sense amplifier, and a current injector. The current injector may be configured to generate multiple current levels and may be operable to controllably select one of the current levels to either source current to or sink current from the input of the sense amplifier.

Abstract translation: 公开了可以允许检测弱数据存储单元的存储器的实施例，或者可以允许在可以代表晶体管老化的影响的条件下操作数据存储单元。 存储器可以包括数据存储单元，列多路复用器，读出放大器和电流注入器。 电流注入器可以被配置为产生多个电流电平，并且可以可操作以可控地选择电流电平中的一个，以从感测放大器的输入端到源电流或从其中吸收电流。

公开(公告)号：US08780650B2

公开(公告)日：2014-07-15

申请号：US14024017

申请日：2013-09-11

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C7/22 ,  G11C7/00 ,  G11C7/02

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

公开(公告)号：US09013933B2

公开(公告)日：2015-04-21

申请号：US14294318

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C7/22 ,  G11C11/418 ,  G11C29/12 ,  G11C29/50 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

公开(公告)号：US20140269025A1

公开(公告)日：2014-09-18

申请号：US14294318

申请日：2014-06-03

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C29/50 ,  G11C7/06 ,  G11C11/418

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

公开(公告)号：US20140010030A1

公开(公告)日：2014-01-09

申请号：US14024017

申请日：2013-09-11

Applicant: Apple Inc.

Inventor： Michael R. Seningen ,  Michael E. Runas

IPC: G11C7/06

CPC classification number: G11C11/418 ,  G11C7/06 ,  G11C7/1051 ,  G11C29/1201 ,  G11C29/50 ,  G11C29/50016 ,  G11C2029/1204 ,  G11C2029/5002

Abstract: Embodiments of a memory are disclosed that may reduce the likelihood of a miss-read while reading a weak data storage cell. The memory may include a number of data storage cells, a column multiplexer, a first sense amplifier and a second sense amplifier, and an output circuit. The gain level of the first sense amplifier may be higher than the gain level of the second sense amplifier. The output circuit may include a multiplexer and the multiplexer may be operable to controllably select one of the outputs of the first and second sense amplifiers and pass the value of the selected sense amplifier. The output circuit may include a node that couples the outputs of the first and second sense amplifiers and the outputs of the first and second sense amplifiers may be able to be set to a high impedance state.

Abstract translation: 公开了一种存储器的实施例，其可以在读取弱数据存储单元时降低读取错误的可能性。 存储器可以包括多个数据存储单元，列多路复用器，第一读出放大器和第二读出放大器以及输出电路。 第一读出放大器的增益电平可以高于第二读出放大器的增益电平。 输出电路可以包括多路复用器，并且多路复用器可以可操作地可控地选择第一和第二读出放大器的输出之一并传递所选择的读出放大器的值。 输出电路可以包括耦合第一和第二读出放大器的输出的节点，并且第一和第二读出放大器的输出可以被设置为高阻抗状态。

公开(公告)号：US20130141073A1

公开(公告)日：2013-06-06

申请号：US13755403

申请日：2013-01-31

Applicant: APPLE INC.

Inventor： Michael E. Runas ,  Michael R. Seningen

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H03K19/0019

Abstract: This disclosure describes a time varying power supply that may include a resonator circuit comprising an inductor having first and second terminals, a first capacitor coupled to the first terminal, and a second capacitor coupled to the second terminal, where the first capacitor produces a first time varying power supply output and wherein the second capacitor produces a second time varying power supply output. The time varying power supply may further include an exciter circuit comprising a first PFET and a first NFET coupled to the first terminal and a second PFET and a second NFET coupled to the second terminal. The first and second PFETs and the first and second NFETs may be coupled to a corresponding one of four non-overlapping clock phases.

Abstract translation: 本公开描述了时变电源，其可以包括谐振器电路，其包括具有第一和第二端子的电感器，耦合到第一端子的第一电容器和耦合到第二端子的第二电容器，其中第一电容器产生第一次 变化的电源输出，并且其中第二电容器产生第二时变电源输出。 时变电源还可以包括激励器电路，其包括耦合到第一端子的第一PFET和第一NFET以及耦合到第二端子的第二PFET和第二NFET。 第一和第二PFET以及第一和第二NFET可以耦合到四个非重叠时钟相位中的对应的一个。