公开(公告)号：US20220231673A1

公开(公告)日：2022-07-21

申请号：US17150888

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Qi Ye ,  Ajay Bhatia ,  Vivekanandan Venugopal

IPC: H03K3/037 ,  H03K3/012 ,  H03K3/356 ,  H03K3/3562

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

公开(公告)号：US20210344344A1

公开(公告)日：2021-11-04

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K19/094 ,  G06F1/10 ,  H03K17/284

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US11139803B1

公开(公告)日：2021-10-05

申请号：US17030163

申请日：2020-09-23

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia

IPC: H03K3/037 ,  H03K5/135 ,  H03K3/0233 ,  H03K3/3562 ,  H03K3/289

Abstract: Systems, apparatuses, and methods for implementing low-power flip-flops with balanced clock-to-Q delay are described. A flip-flop includes a primary latch, an upper secondary latch, and a lower secondary latch. The primary latch transmits a data value from an input port to a first node when transparent. The upper secondary latch pulls up a second node when transparent and when the first node is equal to a first value. The second node is a prebuffered data output of the flip-flop. The lower secondary latch pulls down the second node when transparent and when the first node is equal to a second value different from the first value. To ensure the flip-flop has a balanced clock-to-Q delay, a first set of clock signals coupled to transistor gates of the primary latch are delayed with respect to a second set of clock signals coupled to transistor gates of the upper secondary latch.

公开(公告)号：US10581412B1

公开(公告)日：2020-03-03

申请号：US16369072

申请日：2019-03-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

公开(公告)号：US11496120B2

公开(公告)日：2022-11-08

申请号：US17150888

申请日：2021-01-15

Applicant: Apple Inc.

Inventor： Qi Ye ,  Ajay Bhatia ,  Vivekanandan Venugopal

IPC: H03K3/037 ,  H03K3/3562 ,  H03K3/356 ,  H03K3/012

Abstract: A flip-flop with glitch protection is disclosed. The flip-flop includes a differential amplifier circuit that generates amplifier output signals based on an input data and clock signals and precharges a true data node when a clock signal is inactive. A latch circuit is coupled to the differential amplifier and includes a latch node. Responsive to a current value of the input data signal having a first logic state, the latch node is set at a logic value equivalent to the precharged value during an active phase of the clock signal. Responsive to the current value of the input data signal having a second logic state complementary to the first, during the active phase of the clock signal, the latch circuit causes the latch node to be set to a logic value complementary to the precharged value, using the clock signal and the current value of the input data signal.

公开(公告)号：US11258446B2

公开(公告)日：2022-02-22

申请号：US16862071

申请日：2020-04-29

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Shuyan Lei ,  Wenhao Li ,  Hemangi U. Gajjewar

IPC: H03K3/017 ,  H03K5/04 ,  H03K7/08 ,  H03K19/094 ,  H03K17/284 ,  G06F1/10

Abstract: Systems, apparatuses, and methods for implementing a high-performance clock-gating circuit are described. A first pull-down stack receives enable and pulse signals on gates of N-type transistors which pull down an output node when the enable and pulse signals are both high. A pull-up transistor coupled to the output node receives a clock signal which turns off the pull-up transistor when the clock signal is high. A first pull-up stack receives the inverted pulse signal and the enable signal on gates of P-type transistors to cause the output node to be high when the enable signal and inverted pulse signal are low. A second pull-up stack maintains a high voltage on the output node after the pulse event has ended but while the clock signal is still high. A second pull-down stack maintains a low voltage on the output node after the pulse event but while the clock remains high.

公开(公告)号：US20200313660A1

公开(公告)日：2020-10-01

申请号：US16804675

申请日：2020-02-28

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia ,  Wenhao Li

IPC: H03K3/037 ,  H03K19/0185

Abstract: Techniques are disclosed relating to level-shifting circuitry and time borrowing across voltage domains. In disclosed embodiments, an apparatus includes pulse circuitry, latch circuitry, pull circuitry, and feedback circuitry. The pulse circuitry is configured to generate a pulse signal in response to an active clock edge. The latch circuitry is configured to store a value of an input signal, where the input signal has a first voltage level. The pull circuitry is configured to drive, during the pulse signal, an output of the latch circuitry to match a logical value of the input signal at a second, different voltage level. This may allow the input signal to change during the pulse, enabling time borrowing. The feedback circuitry is configured to maintain the output of the latch circuitry at the second voltage level after the pulse signal.

公开(公告)号：US10270433B1

公开(公告)日：2019-04-23

申请号：US15939156

申请日：2018-03-28

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal

IPC: G06F1/04 ,  H03K3/3562 ,  H03K19/096 ,  H03K3/3568 ,  G01R31/317

Abstract: In various embodiments, a master-slave clock generation circuit may include a first delay circuit, a second delay circuit, a first tristate inverter, and a second tristate inverter. The first delay circuit may delay a clock signal and output a slave clock signal and a delayed clock signal. The first tristate inverter may selectively invert the clock signal based on a scan enable signal. The second tristate inverter may selectively invert the delayed clock signal based on the scan enable signal. The second delay circuit may delay a signal received from the first tristate inverter, the second tristate inverter, or both, and output a master clock signal. As a result, the master-slave clock generation circuit may be configured to output a master clock signal and a slave clock signal having differing sets of relative timing characteristics depending on whether the scan enable signal is asserted.

公开(公告)号：US10187061B1

公开(公告)日：2019-01-22

申请号：US15625642

申请日：2017-06-16

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Kumar Bhatia ,  Michael R. Seningen

IPC: H03K19/0185 ,  H03K19/00 ,  H03K5/08 ,  H03K3/037

Abstract: An apparatus and method for operating a level shifter circuit that receives an input signal of interderminate voltage level is disclosed. The level shifter circuit may receive the input signal from a circuit block coupled to a first power supply signal, and generate an output signal using a second power supply signal, different than the first power supply signal. The level shifter circuit may clamp a storage node included in the level shifter circuit, and isolated at least one circuit path included in the level shifter circuit in response to a determination that an isolation signal has been enabled.

公开(公告)号：US11579642B2

公开(公告)日：2023-02-14

申请号：US17411491

申请日：2021-08-25

Applicant: Apple Inc.

Inventor： Vivekanandan Venugopal ,  Ajay Bhatia

IPC: G05F1/46 ,  G01R21/133 ,  G04F10/00

Abstract: A power detection circuit for detecting powering down of a voltage domain in an integrated circuit is disclosed. The power detection circuit is placed in or near the voltage domain in the integrated circuit to provide power detection on the integrated circuit. The power detection circuit detects powering down of the voltage domain to provide an isolation enable signal to another voltage domain that interfaces with the powering down voltage domain. The isolation enable signal may be used by an isolation cell coupled to the non-powering down voltage domain to prevent corrupted logic being received from the powering down voltage domain.