-
公开(公告)号：US20190080732A1
公开(公告)日：2019-03-14
申请号：US16055570
申请日：2018-08-06
发明人： Cristinel Zonte , Vijay Raghavan , Iulian Gradinariu , Gary Peter Moscaluk , Roger Jay Bettman , Vineet Argrawal , Samuel Leshner
CPC分类号： G11C7/22 , G11C5/145 , G11C5/148 , G11C8/08 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C16/32
摘要： A method for driving a non-volatile memory system is disclosed. A standby detection circuit detects whether the nonvolatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit reduces bias currents provided to drivers of the non-volatile memory system in a standby mode. The non-volatile memory system is operated in the standby mode after the bias currents have been reduced, where an output signal indicating the standby mode is maintained until a read instruction is detected.
-
公开(公告)号：US09627016B2
公开(公告)日：2017-04-18
申请号：US14978733
申请日：2015-12-22
发明人： Vineet Agrawal , Roger Bettman , Samuel Leshner
CPC分类号： G11C7/18 , G06F12/023 , G06F2212/1044 , G11C5/147 , G11C7/06 , G11C7/1015 , G11C7/12 , G11C7/22 , G11C2207/2209 , G11C2207/2281 , G11C2207/229
摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
-
公开(公告)号：US09449655B1
公开(公告)日：2016-09-20
申请号：US14966990
申请日：2015-12-11
发明人： Cristinel Zonte , Vijay Raghavan , Iulian C. Gradinariu , Gary Peter Moscaluk , Roger Bettman , Vineet Argrawal , Samuel Leshner
CPC分类号： G11C7/22 , G11C5/145 , G11C5/148 , G11C8/08 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C16/32
摘要： Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
摘要翻译： 公开了用于在备用操作条件下驱动非易失性存储器件的系统和方法。 备用检测电路检测非易失性存储器系统是否处于待机状态。 响应于确定非易失性存储器系统处于待机状态，偏置控制电路在备用模式下向非易失性存储器系统的驱动器提供偏置电流。
-
公开(公告)号：US10020034B2
公开(公告)日：2018-07-10
申请号：US15463702
申请日：2017-03-20
发明人： Vineet Agrawal , Roger Bettman , Samuel Leshner
CPC分类号： G11C7/18 , G06F12/023 , G06F2212/1044 , G11C5/147 , G11C7/06 , G11C7/1015 , G11C7/12 , G11C7/22 , G11C2207/2209 , G11C2207/2281 , G11C2207/229
摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
-
公开(公告)号：US20170249978A1
公开(公告)日：2017-08-31
申请号：US15463702
申请日：2017-03-20
发明人： Vineet Agrawal , Roger Bettman , Samuel Leshner
CPC分类号： G11C7/18 , G06F12/023 , G06F2212/1044 , G11C5/147 , G11C7/06 , G11C7/1015 , G11C7/12 , G11C7/22 , G11C2207/2209 , G11C2207/2281 , G11C2207/229
摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
-
公开(公告)号：US10062423B2
公开(公告)日：2018-08-28
申请号：US15268315
申请日：2016-09-16
发明人： Cristinel Zonte , Vijay Raghavan , Iulian C. Gradinariu , Gary Peter Moscaluk , Roger Bettman , Vineet Argrawal , Samuel Leshner
CPC分类号： G11C7/22 , G11C5/145 , G11C5/148 , G11C8/08 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C16/32
摘要： Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
-
公开(公告)号：US20170098468A1
公开(公告)日：2017-04-06
申请号：US15268315
申请日：2016-09-16
发明人： Cristinel Zonte , Vijay Raghavan , Iulian C. Gradinariu , Gary Peter Moscaluk , Roger Bettman , Vineet Argrawal , Samuel Leshner
CPC分类号： G11C7/22 , G11C5/145 , G11C5/148 , G11C8/08 , G11C16/0483 , G11C16/26 , G11C16/30 , G11C16/32
摘要： Systems and methods for driving a non-volatile memory device in a standby operating condition are disclosed. A standby detection circuit detects whether the non-volatile memory system is in a standby condition. In response to determining that the non-volatile memory system is in a standby condition, a bias control circuit provides bias currents to drivers of the non-volatile memory system in a standby mode.
-
8.发明申请公开(公告)号：US20170076766A1
公开(公告)日：2017-03-16
申请号：US14978733
申请日：2015-12-22
发明人： Vineet Agrawal , Roger Bettman , Samuel Leshner
CPC分类号： G11C7/18 , G06F12/023 , G06F2212/1044 , G11C5/147 , G11C7/06 , G11C7/1015 , G11C7/12 , G11C7/22 , G11C2207/2209 , G11C2207/2281 , G11C2207/229
摘要： Disclosed herein are systems, methods, and devices for parallel read and write operations. Devices may include a first transmission device coupled to a local bit line and a global bit line associated with a memory unit of a memory array. The first transmission device may be configured to selectively couple the global bit line to the local bit line. The devices may further include a first device coupled to the local bit line and a sense amplifier. The first device may be configured to selectively couple the local bit line to the sense amplifier. The devices may also include a second device coupled to the local bit line and an electrical ground. The second device may be configured to selectively couple the local bit line to the electrical ground.
摘要翻译： 这里公开了用于并行读写操作的系统，方法和装置。 设备可以包括耦合到本地位线的第一传输设备和与存储器阵列的存储器单元相关联的全局位线。 第一传输设备可以被配置为选择性地将全局位线耦合到本地位线。 器件还可以包括耦合到本地位线的第一器件和读出放大器。 第一器件可以被配置为选择性地将局部位线耦合到读出放大器。 该装置还可以包括耦合到本地位线和电接地的第二装置。 第二装置可以被配置为选择性地将局部位线耦合到电接地。
-
-
-
-
-
-
-
搜索结果
8 条记录 (耗时 0.015 秒)
