公开(公告)号：US11494629B2

公开(公告)日：2022-11-08

申请号：US16669855

申请日：2019-10-31

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Xia Li ,  Xiaochun Zhu

IPC: G11C16/08 ,  G06N3/063 ,  G11C11/419 ,  G11C11/412 ,  G11C11/21

Abstract: Certain aspects provide a circuit for in-memory computation. The circuit generally includes a first memory cell, and a first computation circuit. The first computation circuit may include a first switch having a control input coupled to an output of the first memory cell, a second switch coupled between a node of the first computation circuit and the first switch, a control input of the second switch being coupled to a discharge word-line (DCWL), a capacitive element coupled between the node and a reference potential node, a third switch coupled between the node and a read bit-line (RBL), and a fourth switch coupled between the node and an activation (ACT) line.

公开(公告)号：US10964380B1

公开(公告)日：2021-03-30

申请号：US16784149

申请日：2020-02-06

Applicant: QUALCOMM Incorporated

Inventor： Zhongze Wang ,  Yandong Gao ,  Xia Li ,  Ye Lu ,  Xiaochun Zhu ,  Xiaonan Chen

IPC: G11C11/41 ,  G11C11/412 ,  G11C11/56 ,  G11C11/419 ,  H01L27/11 ,  G11C11/418 ,  H01L23/528 ,  H01L23/522 ,  H01L23/00

Abstract: A memory circuit that includes a memory bitcell. The memory bitcell includes a six-transistor circuit configuration, a first transistor coupled to the six-transistor circuit configuration, a second transistor coupled to the first transistor, a third transistor coupled to the second transistor, and a capacitor coupled to the second transistor and the third transistor. The memory circuit includes a read word line coupled to the third transistor, a read bit line coupled to the third transistor, and an activation line coupled to the second transistor. The memory bitcell may be configured to operate as a NAND memory bitcell. The memory bitcell may be configured to operate as a NOR memory bitcell.

公开(公告)号：US09842638B1

公开(公告)日：2017-12-12

申请号：US15414855

申请日：2017-01-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: G11C29/00 ,  G11C11/16

CPC classification number: G11C11/1697 ,  G11C11/1675 ,  G11C29/021 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

Abstract: Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

公开(公告)号：US09754654B1

公开(公告)日：2017-09-05

申请号：US15414855

申请日：2017-01-25

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Xiaochun Zhu ,  Seung Hyuk Kang

IPC: G11C29/00 ,  G11C11/16

Abstract: Dynamically controlling voltage for access (i.e., read and/or write) operations to magneto-resistive random access memory (MRAM) bit cells to account for process variations is disclosed. An MRAM bit cell process variation measurement circuit (PVMC) is configured to measure process variations in MTJs that affect MTJ resistance, which can change write current at a given fixed supply voltage applied to an MRAM bit cell. The MRAM bit cell PVMC may also be configured to measure process variations in logic circuits representing process variations in access transistors employed in MRAM bit cells. These measured process variations in MTJs and/or logic circuits are used to dynamically determine a supply voltage for access operations to MRAM.

公开(公告)号：US20170077387A1

公开(公告)日：2017-03-16

申请号：US14856372

申请日：2015-09-16

Applicant: QUALCOMM Incorporated

Inventor： Jimmy Jianan Kan ,  Matthias Georg Gottwald ,  Xiaochun Zhu ,  Chando Park ,  Seung Hyuk Kang

IPC: H01L43/02 ,  H01L43/12

CPC classification number: H01L43/12 ,  H01F10/3263 ,  H01F10/3286 ,  H01F41/307 ,  H01L43/08

Abstract: Magnetic Tunnel Junction (MTJ) devices particularly suited for efficient spin-torque-transfer (STT) magnetic random access memory (MRAM) (STT MRAM) are disclosed. In one aspect, a MTJ structure with a reduced thickness first pinned layer provided below a tunnel magneto-resistance (TMR) barrier layer is provided. The first pinned layer provided below the TMR bather layer includes one pinned layer magnetized in only one magnetic orientation. In another aspect, a second pinned layer and a spacer layer are provided above a free layer and the TMR barrier layer in the MTJ. The second pinned layer is magnetized in a magnetic orientation that is anti-parallel to that of the first pinned layer. In yet another aspect, a giant magneto-resistance (GMR) spacer layer is provided as the spacer layer between the second pinned layer and the free layer in the MTJ.

Abstract translation: 公开了特别适用于高效自旋转矩传递（STT）磁随机存取存储器（MRAM）（STT MRAM）的磁隧道结（MTJ）装置。 在一个方面，提供了一种在隧道磁阻（TMR）阻挡层下方提供具有减小厚度的第一固定层的MTJ结构。 在TMR沐浴层下面提供的第一被钉扎层包括仅以一个磁性取向磁化的一个钉扎层。 在另一方面，第二被钉扎层和间隔层设置在自由层上方和MTJ中的TMR阻挡层之上。 第二被钉扎层被磁化成与第一被钉扎层反平行的磁取向。 在另一方面，提供巨磁电阻（GMR）间隔层作为MTJ中的第二被钉扎层和自由层之间的间隔层。

公开(公告)号：US09368715B2

公开(公告)日：2016-06-14

申请号：US14822295

申请日：2015-08-10

Applicant: QUALCOMM Incorporated

Inventor： Kangho Lee ,  Seung Kang ,  Xiaochun Zhu

IPC: G11C11/16 ,  H01L43/08 ,  H01L43/02 ,  G06F17/50 ,  H01L43/12

CPC classification number: H01L43/08 ,  G06F17/5068 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1675 ,  H01L43/02 ,  H01L43/12

Abstract: A memory cell includes a magnetic tunnel junction (MTJ) structure that includes a free layer coupled to a bit line and a pinned layer. A magnetic moment of the free layer is substantially parallel to a magnetic moment of the pinned layer in a first state and substantially antiparallel to the magnetic moment of the pinned layer in a second state. The pinned layer has a physical dimension to produce an offset magnetic field corresponding to a first switching current of the MTJ structure to enable switching between the first state and the second state when a first voltage is applied from the bit line to a source line coupled to an access transistor and a second switching current to enable switching between the second state and the first state when the first voltage is applied from the source line to the bit line.

Abstract translation: 存储单元包括磁隧道结（MTJ）结构，其包括耦合到位线和被钉扎层的自由层。 自由层的磁矩基本上平行于处于第一状态的被钉扎层的磁矩，并且在第二状态下基本上与销钉层的磁矩反平行。 固定层具有物理尺寸以产生对应于MTJ结构的第一开关电流的偏移磁场，以便当第一电压从位线施加到耦合到第一状态的源极线时，能够在第一状态和第二状态之间切换 存取晶体管和第二开关电流，以便当第一电压从源极线施加到位线时，能够在第二状态和第一状态之间切换。

公开(公告)号：US09203013B2

公开(公告)日：2015-12-01

申请号：US13872338

申请日：2013-04-29

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung H. Kang ,  Xiaochun Zhu

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/12 ,  G11C11/15

CPC classification number: H01L43/02 ,  G11C11/15 ,  G11C11/16 ,  G11C11/161 ,  H01L27/222 ,  H01L43/08 ,  H01L43/12

Abstract: An apparatus includes a structure that includes a bottom cap layer surrounding a metal pad. The apparatus also includes a magnetic tunnel junction (MTJ) device that includes a bottom electrode coupled to the structure. The MTJ device includes magnetic tunnel junction layers, a top electrode, and a logic cap layer. The MTJ device is offset with respect to the metal pad.

Abstract translation: 一种装置包括包括围绕金属垫的底盖层的结构。 该装置还包括磁隧道结（MTJ）装置，其包括耦合到该结构的底部电极。 MTJ装置包括磁性隧道结层，顶部电极和逻辑帽层。 MTJ装置相对于金属垫偏移。

公开(公告)号：US20150340101A1

公开(公告)日：2015-11-26

申请号：US14820101

申请日：2015-08-06

Applicant: QUALCOMM Incorporated

Inventor： Xia Li ,  Seung Hyuk Kang ,  Xiaochun Zhu

IPC: G11C17/08

CPC classification number: G11C17/08 ,  G11C7/00 ,  G11C7/12 ,  G11C11/40 ,  G11C11/404 ,  G11C17/16 ,  G11C2211/4016 ,  H01L27/105 ,  H01L27/10802 ,  H01L29/7841

Abstract: A method includes applying a programming voltage to a drain of an access transistor, where a source of the access transistor is coupled to a drain region of a one-time programmable (OTP) device. The method also includes applying a first voltage to a gate of the OTP device and a second voltage to a terminal of the OTP device to bias a channel region of the OTP device, where the first voltage and the second voltage are substantially equal.

Abstract translation: 一种方法包括将编程电压施加到存取晶体管的漏极，其中存取晶体管的源极耦合到一次可编程（OTP）器件的漏极区。 该方法还包括将第一电压施加到OTP器件的栅极，并将第二电压施加到OTP器件的端子以偏置OTP器件的沟道区域，其中第一电压和第二电压基本相等。

公开(公告)号：US09135976B2

公开(公告)日：2015-09-15

申请号：US14104443

申请日：2013-12-12

Applicant: QUALCOMM Incorporated

Inventor： Wenqing Wu ,  Kendrick Hoy Leong Yuen ,  Xiaochun Zhu ,  Seung Hyuk Kang ,  Matthew Michael Nowak ,  Jeffrey Alexander Levin ,  Robert P. Gilmore ,  Nicholas Ka Ming Yu

IPC: G11C11/00 ,  G11C11/16 ,  G11C11/56 ,  G11C11/54

CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/161 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/54 ,  G11C11/5607

Abstract: A probabilistic programming current is injected into a cluster of bi-stable probabilistic switching elements, the probabilistic programming current having parameters set to result in a less than unity probability of any given bi-stable switching element switching, and a resistance of the cluster of bi-stable switching elements is detected. The probabilistic programming current is injected and the resistance of the cluster state detected until a termination condition is met. Optionally the termination condition is detecting the resistance of the cluster of bi-stable switching elements at a value representing a multi-bit data.

Abstract translation: 将概率编程电流注入到双稳定概率开关元件簇中，概率编程电流具有设置为导致任何给定双稳态开关元件切换的小于一概率的参数，以及bi的簇的电阻 - 检测到稳定的开关元件。 注入概率编程电流，并检测到簇状态的电阻，直到满足终止条件。 可选地，终止条件是以表示多位数据的值检测双稳态开关元件群的电阻。

公开(公告)号：US20150071431A1

公开(公告)日：2015-03-12

申请号：US14072634

申请日：2013-11-05

Applicant: QUALCOMM Incorporated

Inventor： Xiaochun Zhu ,  Steven M. Millendorf ,  Xu Guo ,  David M. Jacobson ,  Kangho Lee ,  Seung H. Kang ,  Matthew Michael Nowak

IPC: G11C11/16 ,  H04L9/30

CPC classification number: G11C11/1675 ,  G11C11/161 ,  G11C11/1695 ,  H04L9/0866 ,  H04L9/30 ,  H04L9/3278

Abstract: One feature pertains to a method of implementing a physically unclonable function (PUF). The method includes exposing an array of magnetoresistive random access memory (MRAM) cells to an orthogonal external magnetic field. The MRAM cells are each configured to represent one of a first logical state and a second logical state, and the orthogonal external magnetic field is oriented in an orthogonal direction to an easy axis of a free layer of the MRAM cells to place the MRAM cells in a neutral logical state that is not the first logical state or the second logical state. The method further includes removing the orthogonal external magnetic field to place each of the MRAM cells of the array randomly in either the first logical state or the second logical state.

Abstract translation: 一个特征涉及实现物理不可克隆功能（PUF）的方法。 该方法包括将磁阻随机存取存储器（MRAM）阵列阵列暴露于正交外部磁场。 MRAM单元各自被配置为表示第一逻辑状态和第二逻辑状态之一，并且正交外部磁场定向为与MRAM单元的自由层的容易轴正交的方向，以将MRAM单元置于 不是第一逻辑状态或第二逻辑状态的中性逻辑状态。 该方法还包括去除正交的外部磁场，将阵列的每个MRAM单元随机地置于第一逻辑状态或第二逻辑状态中。