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    Back end of line (BEOL) process corner sensing
    2.
    发明授权
    Back end of line (BEOL) process corner sensing 有权

    公开(公告)号：US11823962B2

    公开(公告)日：2023-11-21

    申请号：US17180652

    申请日：2021-02-19

    Applicant: QUALCOMM Incorporated

    Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

    IPC: H01L21/66 ,  G06F30/398

    CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

    Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

    True random number generator based on period jitter
    3.
    发明授权
    True random number generator based on period jitter 有权

    公开(公告)号：US11334321B2

    公开(公告)日：2022-05-17

    申请号：US16913631

    申请日：2020-06-26

    Applicant: QUALCOMM Incorporated

    Inventor： Rui Li ,  De Lu ,  Venkat Narayanan ,  Srivatsan Chellappa

    IPC: G06F7/58

    Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

    VOLTAGE DROOP CONTROL
    4.
    发明申请
    VOLTAGE DROOP CONTROL 审中-公开

    公开(公告)号：US20180046209A1

    公开(公告)日：2018-02-15

    申请号：US15791226

    申请日：2017-10-23

    Applicant: QUALCOMM Incorporated

    Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

    IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

    CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

    Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

    METHOD AND APPARATUS FOR LOW-LEVEL INPUT SENSE AMPLIFICATION
    5.
    发明申请
    METHOD AND APPARATUS FOR LOW-LEVEL INPUT SENSE AMPLIFICATION 有权
    低电平输入信号放大的方法和装置

    公开(公告)号：US20150269978A1

    公开(公告)日：2015-09-24

    申请号：US14218691

    申请日：2014-03-18

    Applicant: QUALCOMM Incorporated

    Inventor： Chulmin Jung ,  Rui Li ,  Sei Seung Yoon ,  Gregory Ameriada Uvieghara

    IPC: G11C7/06 ,  G11C17/16

    CPC classification number: G11C7/062 ,  G11C17/16 ,  G11C17/18 ,  H03F3/45183 ,  H03F3/45497 ,  H03F2203/45402 ,  H03F2203/45604 ,  H03F2203/45641 ,  H03F2203/45652

    Abstract: A sense amplifier is disclosed that includes an amplifier circuit configured to receive, at an input, an input signal including an input level, the amplifier circuit configured to provide an amplified output signal including a gain with respect to the input level; and a feedback circuit coupled to receive the amplified output signal from the amplifier circuit, the feedback circuit configured to provide, at the input of the amplifier circuit, an adjusted version of the amplified output signal including a modified output magnitude based on common mode feedback.

    Abstract translation: 公开了一种读出放大器，其包括放大器电路，其被配置为在输入端接收包括输入电平的输入信号，放大器电路被配置为提供包括相对于输入电平的增益的放大输出信号; 以及反馈电路，其耦合以从放大器电路接收放大的输出信号，所述反馈电路被配置为在放大器电路的输入处提供包括基于共模反馈的修改的输出幅度的经放大的输出信号的调整版本。

    True single phase clock (TSPC) based latch array
    6.
    发明授权
    True single phase clock (TSPC) based latch array 有权

    公开(公告)号：US11695393B2

    公开(公告)日：2023-07-04

    申请号：US17162647

    申请日：2021-01-29

    Applicant: QUALCOMM Incorporated

    Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

    IPC: H03K3/037 ,  H03K19/20 ,  H04B1/40

    CPC classification number: H03K3/037 ,  H03K19/20 ,  H04B1/40

    Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

    Voltage droop control
    7.
    发明授权
    Voltage droop control 有权

    公开(公告)号：US10133285B2

    公开(公告)日：2018-11-20

    申请号：US15791226

    申请日：2017-10-23

    Applicant: QUALCOMM Incorporated

    Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

    IPC: G05F1/10 ,  G06F1/32 ,  H02M1/32

    Abstract: A computer-readable storage medium for controlling voltage droop storing instructions that, when executed by a processor, cause a device to perform operations including receiving a first voltage to a first input of a first component of a device. The first voltage corresponding to a first logical value causes a first internal power supply of the first component to be charged using an external power supply. The operations further include providing a second voltage to a second input of a second component of the device in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second voltage corresponding to the first logical value causes a second internal power supply of the second component of the device to be charged using the external power supply.

    VOLTAGE DROOP CONTROL
    10.
    发明申请
    VOLTAGE DROOP CONTROL 有权
    电压控制

    公开(公告)号：US20160299517A1

    公开(公告)日：2016-10-13

    申请号：US14684128

    申请日：2015-04-10

    Applicant: QUALCOMM Incorporated

    Inventor： Sanjay Bhagawan Patil ,  Daniel Stasiak ,  Martin Pierre Saint-Laurent ,  Rui Li ,  Bin Liang ,  Sei Seung Yoon ,  Chulmin Jung

    IPC: G05F1/10

    CPC classification number: G05F1/10 ,  G06F1/26 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/329 ,  H02M1/32

    Abstract: Voltage droop control is disclosed. A device includes a first component coupled to an external power supply and a second component coupled to the external power supply. The first component includes a first input configured to receive a first voltage, a first internal power supply configured to be charged by the external power supply in response to the first voltage corresponding to a first logical value, and a voltage droop controller configured to output a second voltage via a first output. The second voltage corresponds to the first logical value in response to a first voltage level of the first internal power supply satisfying a second voltage level. The second component includes a second input configured to receive the second voltage from the first output.

    Abstract translation: 公开了电压下降控制。 一种设备包括耦合到外部电源的第一组件和耦合到外部电源的第二组件。 第一组件包括被配置为接收第一电压的第一输入，被配置为响应于对应于第一逻辑值的第一电压由外部电源充电的第一内部电源;以及电压下降控制器，被配置为输出 经由第一输出的第二电压。 响应于满足第二电压电平的第一内部电源的第一电压电平，第二电压对应于第一逻辑值。 第二组件包括被配置为从第一输出接收第二电压的第二输入。

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