公开(公告)号：US12095459B2

公开(公告)日：2024-09-17

申请号：US17805014

申请日：2022-06-01

Applicant: QUALCOMM Incorporated

Inventor： Kevin Bowles ,  Chirag Maheshwari ,  Divya Gangadharan ,  Venkat Narayanan ,  Masoud Zamani

IPC: H03K19/17736 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/00323 ,  H03K19/17744 ,  H03K19/20

Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

公开(公告)号：US20180006650A1

公开(公告)日：2018-01-04

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K19/0185 ,  H03K19/00 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US11810636B2

公开(公告)日：2023-11-07

申请号：US17574431

申请日：2022-01-12

Applicant: QUALCOMM Incorporated

Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

IPC: G11C7/10

CPC classification number: G11C7/1009 ,  G11C7/1087

Abstract: An aspect of the disclosure relates to a latch array, including: a first set of master latches including a first set of clock inputs configured to receive a master clock, a first set of data inputs configured to receive a first set of data, and a first set of data outputs coupled to a set of bitlines, respectively; a second set of master latches including a second set of clock inputs configured to receive the master clock, a first set of write-bit inputs configured to receive a set of write-bit signals, and a set of write-bit outputs coupled to a set of write-bit lines, respectively; and an array of slave latches, wherein the slave latches in columns of the array include a second set of data inputs coupled to the set of bitlines, and a second set of write-bit inputs coupled to the set of write-bit lines, respectively.

公开(公告)号：US11695393B2

公开(公告)日：2023-07-04

申请号：US17162647

申请日：2021-01-29

Applicant: QUALCOMM Incorporated

Inventor： Rui Li ,  De Lu ,  Venkat Narayanan

IPC: H03K3/037 ,  H03K19/20 ,  H04B1/40

CPC classification number: H03K3/037 ,  H03K19/20 ,  H04B1/40

Abstract: A latch array including a row of master latches coupled to columns of slave latches. Each master latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch an input data, and each slave latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch the data from the master latch, and an inverter including an input coupled to the AOI gate and an output to produce an output data based on the input data. Alternatively, each master latch includes an AND-OR-Inverter (AOI) gate cross-coupled with a NOR gate to receive and latch an input data, and each slave latch includes an OR-AND-Inverter (OAI) gate cross-coupled with a NAND gate to receive and latch the data from the master latch, and an inverter including an input coupled to the OAI gate and an output to produce an output data.

公开(公告)号：US09948303B2

公开(公告)日：2018-04-17

申请号：US15367751

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03L5/00 ,  H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K3/356121 ,  H03K3/356191 ,  H03K19/0013 ,  H03K19/01855 ,  H03K19/0963

Abstract: In one embodiment, a voltage level shifter includes a first p-type metal-oxide-semiconductor (PMOS) transistor having a gate configured to receive an input signal in a first power domain, and a second PMOS transistor, wherein the first and second PMOS transistors are coupled in series between a supply voltage of a second power domain and a node. The voltage level shifter also includes an inverter having an input coupled to the node and an output coupled to a gate of the second PMOS transistor, and a first n-type metal-oxide-semiconductor (NMOS) transistor having a gate configured to receive the input signal in the first power domain, wherein the first NMOS transistor is coupled between the node and a ground.

公开(公告)号：US09859893B1

公开(公告)日：2018-01-02

申请号：US15367706

申请日：2016-12-02

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Rakesh Vattikonda ,  De Lu ,  Ramaprasath Vilangudipitchai ,  Samrat Sinharoy ,  Rui Chen

IPC: H03K3/35 ,  H03K19/00 ,  G09G3/20 ,  H03K19/0185 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/012 ,  H03K3/356113 ,  H03K3/35613 ,  H03K3/356182 ,  H03K19/0013

Abstract: In one embodiment, a voltage level shifter includes a first NOR gate having a first input configured to receive a first input signal in a first power domain, a second input configured to receive an enable signal in a second power domain, a third input, and an output. The voltage level shifter also includes a second NOR gate having a first input configured to receive a second input signal in the first power domain, a second input configured to receive the enable signal in the second power domain, a third input coupled to the output of the first NOR gate, and an output coupled to the third input of the first NOR gate. The first and second NOR gates are powered by a supply voltage of the second power domain.

公开(公告)号：US11823962B2

公开(公告)日：2023-11-21

申请号：US17180652

申请日：2021-02-19

Applicant: QUALCOMM Incorporated

Inventor： Saravanan Marimuthu ,  De Lu ,  Baldeo Sharan Sharma ,  Peeyush Kumar Parkar ,  Venkat Narayanan ,  Rui Li ,  Samy Shafik Tawfik Zaynoun ,  Min Chen ,  David Kidd ,  Amit Patil

IPC: H01L21/66 ,  G06F30/398

CPC classification number: H01L22/14 ,  G06F30/398 ,  H01L22/34

Abstract: Aspects of the disclosure are directed to sensing integrated circuit (IC) Back End Of Line (BEOL) process corners. In one aspect, an apparatus for sensing IC BEOL process corners includes a ring oscillator including a plurality of ring oscillator stages configured to generate an output waveform with a frequency state; and a shield net circuit including a plurality of shield net stages corresponding to the plurality of ring oscillator stages, the shield net circuit having a toggle input. And, a method includes generating an output waveform with a frequency state using a ring oscillator that includes a plurality of ring oscillator stages; modifying a plurality of ring oscillator stage time delays through a coupling between a plurality of shield net stages and the plurality of ring oscillator stages; and selecting the frequency state using a toggle input of a shield net circuit which includes the plurality of shield net stages.

公开(公告)号：US11334321B2

公开(公告)日：2022-05-17

申请号：US16913631

申请日：2020-06-26

Applicant: QUALCOMM Incorporated

Inventor： Rui Li ,  De Lu ,  Venkat Narayanan ,  Srivatsan Chellappa

IPC: G06F7/58

Abstract: A true random number generator (TRNG) for generating a sequence of random numbers of bits is disclosed. The TRNG includes a TRNG cell configured to generate a sequence of bits logically alternating with a mean frequency and with substantially random period jitter; a period monitor configured to generate a first sequence of random bits based on a set of periods of the sequence of logically alternating bits; and a sampling circuit configured to sample the first sequence of random bits in response to a sampling clock to generate a second sequence of random bits.

公开(公告)号：US10038429B1

公开(公告)日：2018-07-31

申请号：US15683691

申请日：2017-08-22

Applicant: QUALCOMM Incorporated

Inventor： Venkat Narayanan ,  Qi Ye ,  Manish Srivastava ,  Venugopal Boynapalli

IPC: H03K3/3562 ,  H03K3/013 ,  H03K3/356

CPC classification number: H03K3/35625 ,  H03K3/013 ,  H03K3/356139

Abstract: A flip-flop is provided that includes a sense-amplifier-based master latch clocked by a first edge of a delayed version of a clock signal. A slave latch includes a cross-coupled pair of logic gates for latching a data output signal responsive to a second edge of the clock signal.

公开(公告)号：US09990984B1

公开(公告)日：2018-06-05

申请号：US15370892

申请日：2016-12-06

Applicant: QUALCOMM Incorporated

Inventor： Dorav Kumar ,  Venkat Narayanan ,  Bilal Zafar ,  Seid Hadi Rasouli ,  Venugopal Boynapalli

IPC: G11C11/4094 ,  G11C11/4076 ,  G06F1/12 ,  G06F1/06

CPC classification number: G11C11/4094 ,  G06F1/06 ,  G06F1/12 ,  G06F13/1689 ,  G11C7/222 ,  G11C11/4076

Abstract: The apparatus provided includes a memory. The memory is configured to receive a memory clock. The apparatus also includes a single stage logic gate configured to generate the memory clock from a reference clock. The memory clock is a gated clock. Additionally, the memory clock has a wider pulse width than the reference clock. In an example, the single stage logic gate comprises a pull-up circuit configured to pull-up the memory clock, and a pull-down circuit coupled to pull-down the memory clock. In an example, the pull-up and the pull-down circuits are configured to be controlled by the reference clock, a delayed reference clock, and a gating signal. An example further includes a delay circuit configured to generate the delayed reference clock from the reference clock. An example further includes a latch configured to generate the gating signal.