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    MIMCAP architecture
    1.
    发明授权
    MIMCAP architecture 有权

    公开(公告)号：US11476186B2

    公开(公告)日：2022-10-18

    申请号：US17081720

    申请日：2020-10-27

    Applicant: QUALCOMM Incorporated

    Inventor： Ramaprasath Vilangudipitchai ,  Gudoor Reddy ,  Samrat Sinharoy ,  Smeeta Heggond ,  Anil Kumar Koduru ,  Kamesh Medisetti ,  Seung Hyuk Kang

    IPC: H01L23/522 ,  H01L27/02

    Abstract: A cell on an IC includes a first set of Mx layer interconnects coupled to a first voltage, a second set of Mx layer interconnects coupled to a second voltage different than the first voltage, and a MIM capacitor structure below the Mx layer. The MIM capacitor structure includes a CTM, a CBM, and an insulator between portions of the CTM and the CBM. The first set of Mx layer interconnects is coupled to the CTM. The second set of Mx layer interconnects is coupled to the CBM. The MIM capacitor structure is between the Mx layer and an Mx-1 layer. The MIM capacitor structure includes a plurality of openings. The MIM capacitor structure is continuous within the cell and extends to at least two edges of the cell. In one configuration, the MIM capacitor structure extends to each edge of the cell.

    Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors
    3.
    发明授权
    Method and apparatus for differential power analysis (DPA) resilience security in cryptography processors 有权

    公开(公告)号：US10164768B1

    公开(公告)日：2018-12-25

    申请号：US15904222

    申请日：2018-02-23

    Applicant: QUALCOMM Incorporated

    Inventor： Ravindraraj Ramaraju ,  Rakesh Vattikonda ,  Samrat Sinharoy ,  De Lu ,  Bo Pang

    IPC: H04L9/00 ,  H03K19/00

    Abstract: In certain aspects, a circuit includes a dynamic differential logic gate having first and second outputs, and a first static differential logic gate having first and second outputs, and first and second inputs coupled to the first and second outputs, respectively, of the dynamic differential logic gate. The dynamic differential logic gate is configured to receive a clock signal and to preset both the first and second outputs of the dynamic differential logic gate to a first preset value during a first phase of the clock signal. The first static differential logic gate is configured to preset both the first and second outputs of the first static differential logic gate to a second preset value when the first preset value is input to both the first and second inputs of the first static differential logic gate.

    Apparatus for design for testability of multiport register arrays
    6.
    发明授权
    Apparatus for design for testability of multiport register arrays 有权

    公开(公告)号：US09941866B2

    公开(公告)日：2018-04-10

    申请号：US15207800

    申请日：2016-07-12

    Applicant: QUALCOMM Incorporated

    Inventor： Rakesh Vattikonda ,  Samrat Sinharoy ,  De Lu

    IPC: H03K3/289 ,  H03K3/037 ,  G01R31/317 ,  G01R31/3185

    CPC classification number: H03K3/0372 ,  G01R31/31704 ,  G01R31/31723 ,  G01R31/318541

    Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus is a register array including first and second flip-flop latch arrays. The first flip-flop latch array includes a first set of master latches, a first set of slave latches coupled to the first set of master latches, and a first address port. The second flip-flop latch array includes a second set of master latches, a second set of slave latches coupled to the second set of master latches, and a second address port. The register array includes an address counter, coupled to the first flip-flop latch array and the second flip-flop latch array. The address counter is shared by the first flip-flop latch array and the second flip-flop latch array and configured to address, in parallel in a test mode, the first flip-flop latch array through the first address port and the second flip-flop latch array through the second address port.

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