公开(公告)号：US11934219B2

公开(公告)日：2024-03-19

申请号：US17707621

申请日：2022-03-29

Applicant: QUALCOMM Incorporated

Inventor： Arvind Jain ,  Divya Gangadharan ,  Muhammad Nasir ,  Hong Dai ,  Madan Krishnappa

IPC: G06F1/06 ,  G01R31/317 ,  H04B1/401

CPC classification number: G06F1/06 ,  G01R31/31727 ,  H04B1/401

Abstract: An aspect of the disclosure relates to an integrated circuit (IC). The IC includes a first set of test clock controllers (TCCs) including a first set of clock outputs, respectively; and a first set of functional cores including a first set of clock inputs coupled to the first set of clock outputs of the first set of TCCs, respectively.

公开(公告)号：US12095459B2

公开(公告)日：2024-09-17

申请号：US17805014

申请日：2022-06-01

Applicant: QUALCOMM Incorporated

Inventor： Kevin Bowles ,  Chirag Maheshwari ,  Divya Gangadharan ,  Venkat Narayanan ,  Masoud Zamani

IPC: H03K19/17736 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/00323 ,  H03K19/17744 ,  H03K19/20

Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

公开(公告)号：US09190405B2

公开(公告)日：2015-11-17

申请号：US14169592

申请日：2014-01-31

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Ohsang Kwon ,  Satyanarayana Sahu ,  Divya Gangadharan ,  Chih-Iung Kao ,  Renukprasad Shreedhar Hiremath ,  Animesh Datta ,  Qi Ye

IPC: H01L27/00 ,  H01L27/088 ,  H01L29/06 ,  G06F17/50 ,  H01L23/528

CPC classification number: H01L27/088 ,  G06F17/5068 ,  G06F17/5072 ,  G06F17/5081 ,  H01L23/528 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/0653 ,  H01L2027/11831 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A CMOS device including a standard cell includes first and second transistors with a gate between the first and second transistors. One active region extends between the first and second transistors and under the gate. In a first configuration, when drains/sources of the first and second transistors on the sides of the gate carry the same signal, the drains/sources are connected together and to the gate. In a second configuration, when a source of the first transistor on a side of the gate is connected to a source voltage and a drain/source of the second transistor on the other side of the gate carries a signal, the source of the first transistor is connected to the gate. In a third configuration, when sources of the first and second transistors on the sides of the gate are connected to a source voltage, the gate floats.

Abstract translation: 包括标准单元的CMOS器件包括在第一和第二晶体管之间具有栅极的第一和第二晶体管。 一个有源区域在第一和第二晶体管之间以及栅极之下延伸。 在第一种配置中，当栅极侧面的第一和第二晶体管的漏极/源极具有相同的信号时，漏极/源极连接在一起并连接到栅极。 在第二配置中，当栅极侧的第一晶体管的源极连接到源极电压时，栅极另一侧的第二晶体管的漏极/源极传送信号时，第一晶体管的源极 连接到门。 在第三种配置中，当栅极侧面的第一和第二晶体管的源极连接到源极电压时，栅极浮动。