公开(公告)号：US10784345B2

公开(公告)日：2020-09-22

申请号：US16781856

申请日：2020-02-04

Applicant: QUALCOMM Incorporated

Inventor： Xiangdong Chen ,  Venugopal Boynapalli ,  Hyeokjin Lim

IPC: H01L29/78 ,  H01L29/06 ,  H01L23/532 ,  H01L23/522 ,  H01L29/66 ,  H01L23/528 ,  H01L27/118 ,  H01L27/02

Abstract: A chip includes a first gate extended along a second lateral direction, a first source electrically coupled to a power rail, and a first metal interconnect extended along a first lateral direction approximately perpendicular to the second lateral direction, wherein the first metal interconnect lies above the first gate and the first source, and the first metal interconnect is configured to electrically couple the first gate to the first source. The chip also includes a second gate extended along the second lateral direction, a second source electrically coupled to the power rail, and a second metal interconnect extended along the first lateral direction, wherein the second metal interconnect lies above the second gate and second source, the second metal interconnect is configured to electrically couple the second gate to the second source, and the first metal interconnect is aligned with the second metal interconnect in the second lateral direction.

公开(公告)号：US10593700B2

公开(公告)日：2020-03-17

申请号：US15855996

申请日：2017-12-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L27/118 ,  H01L23/535 ,  H01L27/02 ,  H01L27/092 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes M1 layer interconnects. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only. The device further includes a M0 layer interconnect. The M0 layer interconnect extends directly over a first gate interconnect and extends in a second direction orthogonal to the first direction only. The M0 layer interconnect is below the M1 layer and is isolated from directly connecting to the first gate interconnect. The device further includes a layer interconnect that is different from the M1 layer interconnects and the M0 layer interconnect. The layer interconnect is connected to the M0 layer interconnect and is directly connected to a second gate electrode.

公开(公告)号：US20190088591A1

公开(公告)日：2019-03-21

申请号：US15707807

申请日：2017-09-18

Applicant: QUALCOMM Incorporated

Inventor： Renukprasad Hiremath ,  Hyeokjin Lim ,  Foua Vang ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H01L23/522 ,  H01L23/528 ,  H01L27/092

Abstract: In certain aspects, a semiconductor die includes a first doped region, a second doped region, and an interconnect formed from a first middle of line (MOL) layer, wherein the interconnect electrically couples the first doped region to the second doped region. The semiconductor die also includes a first metal line formed from a first interconnect metal layer, and a first via electrically coupling the interconnect to the first metal line.

公开(公告)号：US09984029B2

公开(公告)日：2018-05-29

申请号：US14484137

申请日：2014-09-11

Applicant: QUALCOMM Incorporated

Inventor： Kern Rim ,  Stanley Seungchul Song ,  Xiangdong Chen ,  Raymond George Stephany ,  John Jianhong Zhu ,  Ohsang Kwon ,  Esin Terzioglu ,  Choh Fei Yeap

IPC: H01L23/528 ,  G06F13/40 ,  G06F13/42 ,  G06F17/50 ,  H01L27/02

CPC classification number: G06F13/4068 ,  G06F13/4221 ,  G06F17/5068 ,  G06F17/5077 ,  H01L23/528 ,  H01L27/0207 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.

公开(公告)号：US09887209B2

公开(公告)日：2018-02-06

申请号：US14279250

申请日：2014-05-15

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon ,  Foua Vang ,  Stanley Seungchul Song ,  Kern Rim

IPC: H01L21/44 ,  H01L27/118 ,  H01L23/535 ,  H01L27/092 ,  H01L27/02 ,  H01L23/528 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L27/11807 ,  H01L21/823475 ,  H01L21/823871 ,  H01L23/5286 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/092 ,  H01L2027/11874 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A standard cell CMOS device includes metal oxide semiconductor transistors having gates formed from gate interconnects. The gate interconnects extend in a first direction. The device further includes power rails that provide power to the transistors. The power rails extend in a second direction orthogonal to the first direction. The device further includes M1 layer interconnects extending between the power rails. At least one of the M1 layer interconnects is coupled to at least one of the transistors. The M1 layer interconnects are parallel to the gate interconnects and extend in the first direction only.

公开(公告)号：US20170317167A1

公开(公告)日：2017-11-02

申请号：US15650042

申请日：2017-07-14

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L21/762 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L29/0649 ,  H01L21/02282 ,  H01L21/762 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

公开(公告)号：US09773866B2

公开(公告)日：2017-09-26

申请号：US14743143

申请日：2015-06-18

Applicant: QUALCOMM Incorporated

Inventor： Haining Yang ,  Xiangdong Chen

IPC: H01L29/06 ,  H01L23/532 ,  H01L21/02 ,  H01L21/762 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L29/0649 ,  H01L21/02282 ,  H01L21/762 ,  H01L21/768 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329

Abstract: Semiconductor integrated circuits (ICs) employing localized low dielectric constant (low-K) material in inter-layer dielectric (ILD) material for improved speed performance are disclosed. To speed up performance of selected circuits in an IC that would otherwise lower overall speed performance of the IC, low-K dielectric material is employed during IC fabrication. The low-K dielectric material is provided in selected, localized areas of ILD material in which selected circuits are disposed. In this manner, the IC will experience an overall increased speed performance during operation, because circuit components and/or circuit element interconnects of selected circuit(s) that are disposed in the low-K ILD material will experience reduced signal delay. Also, by use of low-K dielectric material in only selected, localized areas of ILD material of selected circuits, mechanical and/or thermal stability concern issues that would arise from use of low-K dielectric material in all of the ILD material in the IC are avoided.

公开(公告)号：US09755618B1

公开(公告)日：2017-09-05

申请号：US15061055

申请日：2016-03-04

Applicant: QUALCOMM Incorporated

Inventor： Seid Hadi Rasouli ,  Xiangdong Chen ,  Venugopal Boynapalli

IPC: H03K3/12 ,  H03K3/012 ,  H03K3/356

CPC classification number: H03K3/012 ,  H03K3/356104 ,  H03K3/35625

Abstract: In one example, the apparatus includes a first AND gate, a second AND gate, a first NOR gate, a second NOR gate, a third NOR gate, a first inverter, and a second inverter. The first AND gate output is coupled to the first NOR gate first input. The first NOR gate output is coupled to the second NOR gate first input. The second NOR gate output is coupled to the first NOR gate second input. The first inverter output is coupled to the first AND gate second input and the second NOR gate second input. The second AND gate first input is coupled to the first inverter output. The third NOR gate first input is coupled to the second NOR gate output. The third NOR gate second input is coupled to the second AND gate output. The second inverter output is coupled to the second AND gate second input.

公开(公告)号：US09640522B1

公开(公告)日：2017-05-02

申请号：US15133143

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Vinod Gupta ,  Xiangdong Chen ,  Triveni Rachapalli

IPC: H01L21/70 ,  H01L27/02 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L23/5283 ,  H01L27/0924 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/6681 ,  H01L2027/11831

Abstract: In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.

公开(公告)号：US09640480B2

公开(公告)日：2017-05-02

申请号：US14723357

申请日：2015-05-27

Applicant: QUALCOMM Incorporated

Inventor： Mukul Gupta ,  Xiangdong Chen ,  Ohsang Kwon

IPC: H01L23/528 ,  H01L27/088 ,  G06F1/10 ,  G06F17/50 ,  H01L27/02 ,  H01L27/118

CPC classification number: H01L23/528 ,  G06F1/10 ,  G06F17/5068 ,  H01L23/5286 ,  H01L27/0207 ,  H01L27/088 ,  H01L27/11807 ,  H01L2027/11875 ,  H01L2027/11879

Abstract: A MOS device includes first, second, third, and fourth interconnects. The first interconnect extends on a first track in a first direction. The first interconnect is configured in a metal layer. The second interconnect extends on the first track in the first direction. The second interconnect is configured in the metal layer. The third interconnect extends on a second track in the first direction. The third interconnect is configured in the metal layer. The second track is parallel to the first track. The third interconnect is coupled to the second interconnect. The second and third interconnects are configured to provide a first signal. The fourth interconnect extends on the second track in the first direction. The fourth interconnect is configured in the metal layer. The fourth interconnect is coupled to the first interconnect. The first and fourth interconnects are configured to provide a second signal different than the first signal.