-
公开(公告)号：US20150301973A1
公开(公告)日：2015-10-22
申请号：US14484137
申请日：2014-09-11
Applicant: QUALCOMM Incorporated
Inventor： Kern RIM , Stanley Seungchul SONG , Xiangdong CHEN , Raymond George Stephany , John Jianhong ZHU , Ohsang KWON , Esin TERZIOGLU , Choh Fei YEAP
CPC classification number: G06F13/4068 , G06F13/4221 , G06F17/5068 , G06F17/5077 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.
Abstract translation: 设计导电互连的方法包括至少部分地基于互连迹线间距和指定单元高度的整数倍来确定残余间隔值。 该方法还包括将剩余间隔分配到互连迹线间距内的至少一个互连迹线宽度或互连迹线空间。
-
公开(公告)号：US09984029B2
公开(公告)日：2018-05-29
申请号：US14484137
申请日：2014-09-11
Applicant: QUALCOMM Incorporated
Inventor： Kern Rim , Stanley Seungchul Song , Xiangdong Chen , Raymond George Stephany , John Jianhong Zhu , Ohsang Kwon , Esin Terzioglu , Choh Fei Yeap
IPC: H01L23/528 , G06F13/40 , G06F13/42 , G06F17/50 , H01L27/02
CPC classification number: G06F13/4068 , G06F13/4221 , G06F17/5068 , G06F17/5077 , H01L23/528 , H01L27/0207 , H01L2924/0002 , H01L2924/00
Abstract: A method of designing conductive interconnects includes determining a residual spacing value based at least in part on an integer multiple of a interconnect trace pitch and a designated cell height. The method also includes allocating the residual spacing to at least one interconnect trace width or interconnect trace space within the interconnect trace pitch.
-
公开(公告)号：US10175571B2
公开(公告)日：2019-01-08
申请号：US15182510
申请日：2016-06-14
Applicant: QUALCOMM Incorporated
Inventor： Xiangdong Chen , Hyeokjin Bruce Lim , Ohsang Kwon , Mickael Malabry , Jingwei Zhang , Raymond George Stephany , Haining Yang , Kern Rim , Stanley Seungchul Song , Mukul Gupta , Foua Vang
Abstract: In an aspect of the disclosure, a method, a computer-readable medium, and an apparatus for assigning feature colors for a multiple patterning process are provided. The apparatus receives integrated circuit layout information including a set of features and an assigned color of a plurality of colors for each feature of a first subset of features of the set of features. In addition, the apparatus performs color decomposition on a second subset of features to assign colors to features in the second subset of features. The second subset of features includes features in the set of features that are not included in the first subset of features with an assigned color.
-
公开(公告)号：US09379058B2
公开(公告)日：2016-06-28
申请号：US14274184
申请日：2014-05-09
Applicant: QUALCOMM Incorporated
Inventor： Stanley Seungchul Song , Zhongze Wang , Ohsang Kwon , Kern Rim , John Jianhong Zhu , Xiangdong Chen , Foua Vang , Raymond George Stephany , Choh Fei Yeap
IPC: H01L29/423 , H01L29/417 , H01L23/528 , H01L23/522 , H01L27/088 , H01L21/768 , H01L27/118
CPC classification number: H01L23/5283 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/5226 , H01L27/088 , H01L29/41775 , H01L29/42312 , H01L2027/11866 , H01L2924/0002 , H01L2924/00
Abstract: A semiconductor device includes a gate and a first active contact adjacent to the gate. Such a device further includes a first stacked contact electrically coupled to the first active contact, including a first isolation layer on sidewalls electrically isolating the first stacked contact from the gate. The device also includes a first via electrically coupled to the gate and landing on the first stacked contact. The first via electrically couples the first stacked contact and the first active contact to the gate to ground the gate.
Abstract translation: 半导体器件包括栅极和邻近栅极的第一有源触点。 这种器件还包括电耦合到第一有源触点的第一堆叠触点，包括在侧壁上电隔离第一堆叠触头与栅极的第一隔离层。 该装置还包括电连接到门的第一通孔和第一堆叠接触件上的着陆。 第一通孔将第一堆叠触点和第一有源触点电耦合到栅极以将栅极接地。
-
-
-
Search Results
4
records
(took 0.01 seconds)
