公开(公告)号：US20170061063A1

公开(公告)日：2017-03-02

申请号：US14839687

申请日：2015-08-28

Applicant: QUALCOMM Incorporated

Inventor： Vinod Gupta ,  Rajiv Mittal ,  Abhishek Chouksey

IPC: G06F17/50

CPC classification number: G06F17/5081 ,  G06F17/5072 ,  G06F17/5077 ,  H01L27/11582 ,  H01L28/00

Abstract: Systems and methods for reducing routing congestion in an integrated circuit allow an integrated circuit floorplan to be modified, for example, after cell placement and global routing. Modifying the floorplan can avoid delays in time to market for the integrated circuit and can avoid increasing the size of the integrated circuit. Reducing routing congestion includes adding routing congestion reduction regions in cell/routing regions of the floorplan. The routing congestion reduction regions may modify how cells can be placed in the region. The routing congestion reduction regions may also modify how connections can be routed in the region. The routing congestion reduction regions may be a halo region that includes modifying preferred routing directions in regions nears edges of hard macros, a hammerhead region that includes laterally expanding the end of the river routing region, and a corner congestion reduction region for use at corners of hard macros.

Abstract translation: 用于减少集成电路中的路由拥塞的系统和方法允许修改集成电路平面图，例如，在小区放置和全局路由之后。 修改平面图可以避免集成电路的上市时间延迟，并且可以避免增加集成电路的尺寸。 减少路由拥塞包括在平面图中的小区/路由区域中添加路由拥塞减少区域。 路由拥塞减少区域可以修改如何将小区放置在该区域中。 路由拥塞减少区域还可以修改如何在该区域中路由连接。 路由拥塞减少区域可以是包括修改在硬宏边缘附近的区域中的优选路由方向的晕圈区域，包括横向扩展河道路区域的端部的锤头区域和用于在 硬宏。

公开(公告)号：US09640522B1

公开(公告)日：2017-05-02

申请号：US15133143

申请日：2016-04-19

Applicant: QUALCOMM Incorporated

Inventor： Satyanarayana Sahu ,  Vinod Gupta ,  Xiangdong Chen ,  Triveni Rachapalli

IPC: H01L21/70 ,  H01L27/02 ,  H01L23/528 ,  G06F17/50

CPC classification number: H01L27/0207 ,  G06F17/5077 ,  H01L23/5283 ,  H01L27/0924 ,  H01L27/11807 ,  H01L28/00 ,  H01L29/6681 ,  H01L2027/11831

Abstract: In an aspect of the disclosure, apparatuses for reducing the cost of using an ECO standard cell library in chip design are provided. Such an apparatus may be a MOS device including several regions. The MOS device may include a pMOS transistor and an nMOS transistor in a first region of the device. The pMOS transistor gate of the pMOS transistor and the nMOS transistor gate of the nMOS transistor may be formed by a gate interconnect extending in a first direction across the device. The MOS device may include several unutilized pMOS transistors and several unutilized nMOS transistors in a second region of the device adjacent to the first region. Fins of the pMOS transistors and the nMOS transistors in the first region may be disconnected from fins of the unutilized pMOS transistors and the unutilized nMOS transistors in the second region.