公开(公告)号：US10163474B2

公开(公告)日：2018-12-25

申请号：US15273606

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Masoud Zamani ,  Bilal Zafar ,  Venkatasubramanian Narayanan

IPC: G11C7/22 ,  H03K5/133 ,  H03K19/20 ,  H03K5/00

Abstract: A memory circuit according to some examples may include a clock delay circuit that use a polarity of a write enable signal to determine an operation (i.e. write or read) on the memory that provides the desired clock latency to the memory. The clock delay circuit may have a low skew portion and a high skew portion. The selection of the high skew portion or low skew portion may depend on the status of the write enable line, such as a polarity or logical value.

公开(公告)号：US10965305B1

公开(公告)日：2021-03-30

申请号：US16793661

申请日：2020-02-18

Applicant: QUALCOMM Incorporated

Inventor： Ravindraraj Ramaraju ,  Elhossin Abdelmonem Elshafey ,  Masoud Zamani ,  Elham Zamanidoost

IPC: H03M1/12 ,  G04F10/00 ,  H03M1/50 ,  H03K19/20 ,  H03K3/03

Abstract: Certain aspects are directed to a time-to-digital converter (TDC) that allows for a more accurate jitter measurement. The TDC generally includes a ring oscillator (RO) having a plurality of taps and configured to generate a plurality of RO signals at the plurality of taps, a counter having an input coupled to an oscillating node, and at least two sampling circuits, each having an input coupled to an output of the counter. In certain aspects, the at least two sampling circuits are configured to sample a count signal at the output of the counter based on at least two of the plurality of RO signals at the plurality of taps.

公开(公告)号：US12095459B2

公开(公告)日：2024-09-17

申请号：US17805014

申请日：2022-06-01

Applicant: QUALCOMM Incorporated

Inventor： Kevin Bowles ,  Chirag Maheshwari ,  Divya Gangadharan ,  Venkat Narayanan ,  Masoud Zamani

IPC: H03K19/17736 ,  H03K19/003 ,  H03K19/20

CPC classification number: H03K19/1774 ,  H03K19/00323 ,  H03K19/17744 ,  H03K19/20

Abstract: In certain aspects, an apparatus includes a first gating circuit having an input and an output, wherein the input of the first gating circuit is configured to receive a first clock signal. The apparatus also includes a delay circuit having an input and an output, wherein the input of the delay circuit is coupled to the output of the first gating circuit. The apparatus further includes a control circuit configured to receive an enable signal, detect a logic state at the output of the delay circuit, and cause the first gating circuit to pass or gate the first clock signal based on the enable signal and the detected logic state at the output of the delay circuit.

公开(公告)号：US20180074126A1

公开(公告)日：2018-03-15

申请号：US15263059

申请日：2016-09-12

Applicant: QUALCOMM Incorporated

Inventor： Bilal Zafar ,  Rakesh Vattikonda ,  De Lu ,  Venkatasubramanian Narayanan ,  Masoud Zamani ,  Joseph Fang

IPC: G01R31/317 ,  G11C7/22 ,  G01R31/3177

CPC classification number: G01R31/31727 ,  G01R31/31704 ,  G01R31/3177 ,  G01R31/318552 ,  G11C7/22

Abstract: An apparatus and method of employing mutually exclusive write and read clocks in scan capture mode for testing digital interfaces. The apparatus includes a first circuit and a first clock generator configured to generate a first clock signal for transferring a test sample from an input to an output of the first circuit in response to the first clock signal during each of a first set of scan capture cycles; a second circuit and a second clock generator configured to generate a second clock signal for transferring the test sample from an input to an output of the second circuit in response to the second clock signal during each of a second set of scan capture cycle; the first clock signal being suppressed during each scan capture cycle of the second set, and the second clock signal being suppressed during each scan capture cycle of the first set.