公开(公告)号：US12058862B2

公开(公告)日：2024-08-06

申请号：US18091728

申请日：2022-12-30

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC: H10B43/27 ,  G11C16/04 ,  H01L29/51 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US11903207B2

公开(公告)日：2024-02-13

申请号：US17750207

申请日：2022-05-20

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H10B43/27 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/04

CPC classification number: H10B43/27 ,  H01L21/8221 ,  H01L27/0688 ,  H01L27/105 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B69/00 ,  G11C16/0483

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US11362106B2

公开(公告)日：2022-06-14

申请号：US17141504

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H01L27/105 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556 ,  G11C16/04

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US12089409B2

公开(公告)日：2024-09-10

申请号：US18339526

申请日：2023-06-22

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Jun Iijima ,  Ryota Katsumata ,  Kazuyuki Higashi

IPC: H01L23/522 ,  H01L23/00 ,  H01L25/065 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/04 ,  G11C16/26

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L24/04 ,  H01L25/0657 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  G11C5/02 ,  G11C16/0483 ,  G11C16/26 ,  H01L24/05 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/05095 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/08145 ,  H01L2224/08146 ,  H01L2224/80201 ,  H01L2224/80894 ,  H01L2224/80895 ,  H01L2924/1304 ,  H01L2924/13091 ,  H01L2924/1434 ,  H01L2224/05624 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/00012 ,  H01L2924/13091 ,  H01L2924/00012 ,  H01L2924/1304 ,  H01L2924/00012 ,  H01L2224/05647 ,  H01L2924/00014

Abstract: According to one embodiment, a semiconductor memory device includes a first memory chip, a circuit chip, and an external connection electrode on a surface of the first memory chip. The first memory chip comprises first conductors stacked via an insulator, and a first pillar passing the first conductors. The circuit chip comprises a substrate, a control circuit, and a second conductor connected to the control circuit, the circuit chip being attached to the first memory chip. The external connection electrode comprises a portion extending from a side of the surface of the first memory chip through the first memory chip and connected to the second conductor. Part of the first conductors is between the external connection electrode and the substrate.

公开(公告)号：US11974439B2

公开(公告)日：2024-04-30

申请号：US17991694

申请日：2022-11-21

Applicant: KIOXIA CORPORATION

Inventor： Tomoo Hishida ,  Sadatoshi Murakami ,  Ryota Katsumata ,  Masao Iwase

IPC: H10B43/35 ,  H01L21/8234 ,  H10B43/27 ,  H10B43/50

CPC classification number: H10B43/35 ,  H01L21/823437 ,  H10B43/27 ,  H10B43/50

Abstract: A semiconductor memory includes a memory cell region that includes multiple memory cells stacked above a semiconductor substrate, first and second dummy regions on opposite sides of the memory cell region, each dummy region including multiple dummy cells stacked above the semiconductor substrate, and a wiring that electrically connects dummy cells of the first and second dummy regions that are at a same level above the semiconductor substrate.

公开(公告)号：US11844218B2

公开(公告)日：2023-12-12

申请号：US17843320

申请日：2022-06-17

Applicant: KIOXIA CORPORATION

Inventor： Yoshiaki Fukuzumi ,  Ryota Katsumata ,  Masaru Kidoh ,  Masaru Kito ,  Hiroyasu Tanaka ,  Yosuke Komori ,  Megumi Ishiduki ,  Hideaki Aochi

IPC: H01L29/51 ,  H10B43/27 ,  G11C16/04 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

CPC classification number: H10B43/27 ,  G11C16/0483 ,  H01L29/513 ,  H10B41/27 ,  H10B43/20 ,  H10B43/40 ,  H10B43/50 ,  H10B99/00 ,  H10B41/20

Abstract: A non-volatile semiconductor storage device has a plurality of memory strings to each of which a plurality of electrically rewritable memory cells are connected in series. Each of the memory strings includes first semiconductor layers each having a pair of columnar portions extending in a vertical direction with respect to a substrate and a coupling portion formed to couple the lower ends of the pair of columnar portions; a charge storage layer formed to surround the side surfaces of the columnar portions; and first conductive layers formed to surround the side surfaces of the columnar portions and the charge storage layer. The first conductive layers function as gate electrodes of the memory cells.

公开(公告)号：US11817428B2

公开(公告)日：2023-11-14

申请号：US17590373

申请日：2022-02-01

Applicant: KIOXIA CORPORATION

Inventor： Masayoshi Tagami ,  Ryota Katsumata ,  Jun Iijima ,  Tetsuya Shimizu ,  Takamasa Usui ,  Genki Fujita

IPC: H01L29/788 ,  H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50

CPC classification number: H01L25/0657 ,  H01L24/08 ,  H01L25/50 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/05025 ,  H01L2224/05147 ,  H01L2224/05571 ,  H01L2224/08146 ,  H01L2225/06544 ,  H01L2225/06565 ,  H01L2224/05571 ,  H01L2924/00012 ,  H01L2224/05147 ,  H01L2924/00014

Abstract: A memory device includes a first memory cell array, a second memory cell array disposed in a first direction with respect to the first memory cell array, a first contact plug extending in the first direction through the first memory cell array, and a second contact plug extending in the first direction through the second memory cell array. The first memory cell array includes first electrode layers stacked in a first direction, and a first semiconductor pillar extending through the first electrode layers in the first direction. The second memory cell array including second electrode layers stacked in the first direction, and a second semiconductor pillar extending in the first direction through the second electrode layers. The first contact plug is electrically connected to the first semiconductor pillar, and the second contact plug is electrically connected to the second semiconductor pillar and the first contact plug.

公开(公告)号：USRE49152E1

公开(公告)日：2022-07-26

申请号：US16926273

申请日：2020-07-10

Applicant: Kioxia Corporation

Inventor： Ryota Katsumata ,  Hideaki Aochi ,  Hiroyasu Tanaka ,  Masaru Kito ,  Yoshiaki Fukuzumi ,  Masaru Kidoh ,  Yosuke Komori ,  Megumi Ishiduki ,  Junya Matsunami ,  Tomoko Fujiwara ,  Ryouhei Kirisawa ,  Yoshimasa Mikajiri ,  Shigeto Oota

IPC: G11C11/14 ,  H01L27/11578 ,  G11C16/04 ,  G11C16/06 ,  H01L27/11565 ,  H01L27/11582

Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a substrate, a stacked body, a semiconductor pillar, a charge storage film, and a drive circuit. The stacked body is provided on the substrate. The stacked body includes a plurality of insulating films alternately stacked with a plurality of electrode films. A through-hole is made in the stacked body to align in a stacking direction. The semiconductor pillar is buried in an interior of the through-hole. The charge storage film is provided between the electrode film and the semiconductor pillar. The drive circuit supplies a potential to the electrode film. The diameter of the through-hole differs by a position in the stacking direction. The drive circuit supplies a potential to reduce a potential difference with the semiconductor pillar as a diameter of the through-hole piercing the electrode film decreases.

公开(公告)号：US11374021B2

公开(公告)日：2022-06-28

申请号：US17141534

申请日：2021-01-05

Applicant: Kioxia Corporation

Inventor： Masaru Kito ,  Hideaki Aochi ,  Ryota Katsumata ,  Akihiro Nitayama ,  Masaru Kidoh ,  Hiroyasu Tanaka ,  Yoshiaki Fukuzumi ,  Yasuyuki Matsuoka ,  Mitsuru Sato

IPC: H01L27/11 ,  H01L27/11582 ,  H01L21/822 ,  H01L27/06 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573 ,  H01L27/11578 ,  H01L27/11556 ,  G11C16/04

Abstract: A nonvolatile semiconductor memory device that have a new structure are provided, in which memory cells are laminated in a three dimensional state so that the chip area may be reduced. The nonvolatile semiconductor memory device of the present invention is a nonvolatile semiconductor memory device that has a plurality of the memory strings, in which a plurality of electrically programmable memory cells is connected in series. The memory strings comprise a pillar shaped semiconductor; a first insulation film formed around the pillar shaped semiconductor; a charge storage layer formed around the first insulation film; the second insulation film formed around the charge storage layer; and first or nth electrodes formed around the second insulation film (n is natural number more than 1). The first or nth electrodes of the memory strings and the other first or nth electrodes of the memory strings are respectively the first or nth conductor layers that are spread in a two dimensional state.

公开(公告)号：US12232325B2

公开(公告)日：2025-02-18

申请号：US17462854

申请日：2021-08-31

Applicant: Kioxia Corporation

Inventor： Keisuke Nakatsuka ,  Yoshitaka Kubota ,  Tetsuaki Utsumi ,  Yoshiro Shimojo ,  Ryota Katsumata

IPC: H10B43/10 ,  H10B41/10 ,  H10B41/20 ,  H10B41/35 ,  H10B41/41 ,  H10B43/20 ,  H10B43/35 ,  H10B43/40

Abstract: A semiconductor storage device includes a first conductive layer, a second conductive layer, a third conductive layer, a contact plug, a memory trench extending between the second conductive layer and the third conductive layer. The memory trench is formed around the contact plug, and surrounds a first area in which the contact plug is disposed. A second area is separated from the first area and includes a pillar penetrating the first conductive layer. The second conductive layer extends between the first and second areas, and is connected to the first conductive layer. The third conductive layer is on the opposite side of the first area to the second area, and is connected to the first conductive layer.