公开(公告)号：US20230093076A1

公开(公告)日：2023-03-23

申请号：US17677654

申请日：2022-02-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Seunggeol NAM ,  Jinseong HEO ,  Sanghyun JO ,  Dukhyun CHOE

IPC: H01L29/78 ,  H01L21/66 ,  H01L29/51 ,  H01L29/66

Abstract: Provided are a ferroelectric semiconductor device and a method of extracting a defect density of the same. A ferroelectric electronic device includes a first layer, an insulating layer including a ferroelectric layer and a first interface that is adjacent to the first layer, and an upper electrode over the insulating layer, wherein the insulating layer has a bulk defect density of 1016 cm−3eV−1 or more and an interface defect density of 1010 cm−2eV−1 or more.

公开(公告)号：US20230275150A1

公开(公告)日：2023-08-31

申请号：US18168699

申请日：2023-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjae LEE ,  Jinseong HEO ,  Seunggeol NAM ,  Taehwan MOON ,  Hagyoul BAE

IPC: H01L29/78 ,  H01L29/76

CPC classification number: H01L29/78391 ,  H01L29/7606

Abstract: A semiconductor device may include a semiconductor substrate including a dopant having a polarity; a channel layer on the semiconductor substrate and including majority carriers having a polarity opposite to a polarity of the semiconductor substrate; a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. A doping concentration of the semiconductor substrate may be less than a concentration of the majority carrier of the channel layer.

公开(公告)号：US20220173099A1

公开(公告)日：2022-06-02

申请号：US17491841

申请日：2021-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwook KIM ,  Seunggeol NAM ,  Taehwan MOON ,  Kwanghee LEE ,  Jinseong HEO ,  Hagyoul BAE ,  Yunseong LEE

IPC: H01L27/092 ,  H01L27/11 ,  H01L29/24 ,  H01L29/51 ,  H01L29/78 ,  H01L29/786

Abstract: Provided is a semiconductor device including a first semiconductor transistor including a semiconductor channel layer, and a metal-oxide semiconductor channel layer, and having a structure in which a second semiconductor transistor is stacked on the top of the first semiconductor transistor. A gate stack of the second semiconductor transistor and the top of a gate stack of the first semiconductor transistor may overlap by greater than or equal to 90%. The first semiconductor transistor and the second semiconductor transistor may have a similar level of operation characteristics.

公开(公告)号：US20220140148A1

公开(公告)日：2022-05-05

申请号：US17515984

申请日：2021-11-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Sangwook KIM ,  Hagyoul BAE ,  Taehwan MOON ,  Yunseong LEE

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/51

Abstract: Provided is a ferroelectric semiconductor device including a source and a drain having different polarities. The ferroelectric semiconductor may include a ferroelectric including zirconium oxide (ZrO2), hafnium oxide (HfO2), and/or hafnium-zirconium oxide (HfxZr1−xO, 0

公开(公告)号：US20240266445A1

公开(公告)日：2024-08-08

申请号：US18638923

申请日：2024-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00

CPC classification number: H01L29/86 ,  H10B69/00 ,  H10K10/50 ,  H10K19/00 ,  H10K19/201

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20240265967A1

公开(公告)日：2024-08-08

申请号：US18621853

申请日：2024-03-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE

IPC: G11C15/04

CPC classification number: G11C15/046

Abstract: Disclosed are a non-volatile content addressable memory device having a simple cell configuration and/or an operating method thereof. The non-volatile content addressable memory device includes a plurality of unit cells, wherein each of the plurality of unit cells consists of or includes a first ferroelectric transistor and a second ferroelectric transistor The first and second ferroelectric transistors are of different types such as different electrical types from each other. The first and second ferroelectric transistors may be connected in series or in parallel to each other. The first and second ferroelectric transistors may share one word line and one match line. The first and second ferroelectric transistors may share one search line. One of the first and second ferroelectric transistors may be connected to a search line and the other one may be connected to a bar search line. The first and second ferroelectric transistors may share one match line.

公开(公告)号：US20230141173A1

公开(公告)日：2023-05-11

申请号：US17983856

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunggeol NAM ,  Hagyoul BAE ,  Jinseong HEO

IPC: H01L29/78 ,  H01L27/118 ,  H01L29/49 ,  H01L29/423 ,  H01L29/786

CPC classification number: H01L29/78391 ,  H01L27/11807 ,  H01L29/4908 ,  H01L29/42392 ,  H01L29/78645 ,  H01L29/78696 ,  H01L2027/11838

Abstract: According to various example embodiments, a semiconductor element includes: a channel layer including a semiconductor material; a p-type semiconductor layer and an n-type semiconductor layer apart from each other with the channel layer therebetween, a paraelectric layer on a first area of the channel layer, a ferroelectric layer on a second area different from the first area of the channel area, and having a polarization state due to a voltage applied from an external source, a first gate electrode on the paraelectric layer, a second gate electrode on the ferroelectric layer, and an insulating layer between the first gate electrode and the second gate electrode, and electrically separating the first gate electrode and the second gate electrode from each other.

公开(公告)号：US20220173255A1

公开(公告)日：2022-06-02

申请号：US17461034

申请日：2021-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinseong HEO ,  Taehwan MOON ,  Hagyoul BAE ,  Seunggeol NAM ,  Sangwook KIM ,  Kwanghee LEE

IPC: H01L29/86 ,  H01L27/115 ,  H01L51/05 ,  H01L27/28

Abstract: A semiconductor apparatus includes a plurality of semiconductor devices. The semiconductor devices each include a ferroelectric layer, a conductive metal oxide layer, and a semiconductor layer, between two electrodes. The conductive metal oxide layer may be between the ferroelectric layer and the semiconductor layer. The ferroelectric layer, the conductive metal oxide layer, and the semiconductor layer may all include a metal oxide. The conductive metal oxide layer may include one or more materials selected from the group consisting of an indium oxide, a zinc oxide, a tin oxide, and any combination thereof.

公开(公告)号：US20230186086A1

公开(公告)日：2023-06-15

申请号：US18063936

申请日：2022-12-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehwan MOON ,  Jinseong HEO ,  Seunggeol NAM ,  Hagyoul BAE ,  Hyunjae LEE

IPC: G06N3/08 ,  G06N3/04

CPC classification number: G06N3/08 ,  G06N3/04

Abstract: Provided is a neural network device including a plurality of word lines extending in a first direction, a plurality of bit lines extending in a second direction intersecting the first direction, and a plurality of memory cells arranged at points where the plurality of word lines and the plurality of bit lines intersect one another. Each of the plurality of memory cells includes at least two ferroelectric memories connected in parallel along a word line corresponding to each of the plurality of memory cells.

公开(公告)号：US20230155026A1

公开(公告)日：2023-05-18

申请号：US17986237

申请日：2022-11-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hagyoul BAE ,  Dukhyun CHOE ,  Jinseong HEO ,  Yunseong LEE ,  Seunggeol NAM ,  Hyunjae LEE

IPC: H01L29/78 ,  H01L27/108 ,  H01L27/24 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L27/10805 ,  H01L27/2436 ,  H01L29/516 ,  H01L29/7833 ,  H01L29/6684

Abstract: Provided are a semiconductor device and a semiconductor apparatus including the semiconductor device. The semiconductor device includes a substrate having a channel layer comprising a dopant, a ferroelectric layer on the channel layer; and a gate on the ferroelectric layer. The channel layer has a doping concentration of 1×1015 cm−3 to 1×1021 cm−3.