公开(公告)号：US20230317177A1

公开(公告)日：2023-10-05

申请号：US18205915

申请日：2023-06-05

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/30 ,  G11C16/0483 ,  G11C16/32 ,  G11C16/08 ,  G11C16/26

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving an address indicating a region in the memory cell array, and a control circuit controlling operations of the memory cell array. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US20250046384A1

公开(公告)日：2025-02-06

申请号：US18923698

申请日：2024-10-23

Applicant: Kioxia Corporation

Inventor： Akio SUGAHARA ,  Takaya HANDA ,  Ryosuke ISOMURA ,  Kazuto UEHARA ,  Junichi SATO ,  Norichika ASAOKA ,  Masashi YAMAOKA ,  Bushnaq SANAD ,  Yuzuru SHIBAZAKI ,  Noriyasu KUMAZAKI ,  Yuri TERADA

IPC: G11C16/30 ,  G11C16/04 ,  G11C16/08 ,  G11C16/12 ,  G11C16/26 ,  G11C16/32 ,  H10B69/00

Abstract: A memory device includes a memory cell array, a voltage generation circuit generating one or more voltages supplied to the memory cell array, an input/output circuit receiving a first command and an address indicating a region in the memory cell array, and a control circuit controlling a read operation to the memory cell array based on the first command. The control circuit supplies a non-selection voltage of the voltages before a ready/busy signal changes from a ready state to a busy state.

公开(公告)号：US20230253045A1

公开(公告)日：2023-08-10

申请号：US18299505

申请日：2023-04-12

Applicant: Kioxia Corporation

Inventor： Sanad BUSHNAQ ,  Noriyasu KUMAZAKI ,  Masashi YAMAOKA

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/14 ,  G11C16/24 ,  H10B41/27

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/24 ,  H10B41/27 ,  G11C16/10

Abstract: According to one embodiment, a semiconductor storage device includes a first memory string including a first memory transistor, a first word line connected to a gate electrode of the first memory transistor, a source line connected to one end of the memory string, and a first connection transistor connected between the first word line and the source line.

公开(公告)号：US20210233895A1

公开(公告)日：2021-07-29

申请号：US17007797

申请日：2020-08-31

Applicant: KIOXIA CORPORATION

Inventor： Masashi YAMAOKA ,  Kazuhiro TOMISHIGE ,  Naoki YAMAMOTO

IPC: H01L25/065 ,  G11C5/06 ,  G11C16/04 ,  H01L23/538

Abstract: A semiconductor storage device includes a substrate, a plurality of conductive layers arranged in a first direction intersecting a surface of the substrate, and a semiconductor layer extending in the first direction and penetrating the plurality of conductive layers. The plurality of conductive layers includes a first conductive layer and a second conductive layer that are adjacent to each other, a third conductive layer and a fourth conductive layer that are adjacent to each other, and a fifth conductive layer and a sixth conductive layer that are adjacent to each other. When a distance between the first conductive layer and the second conductive layer in the first direction is a first distance, a distance between the third conductive layer and the fourth conductive layer in the first direction is a second distance, and a distance between the fifth conductive layer and the sixth conductive layer in the first direction is a third distance, the second distance is smaller than the first distance, and the third distance is smaller than the second distance.