公开(公告)号：US20230309321A1

公开(公告)日：2023-09-28

申请号：US17898255

申请日：2022-08-29

Applicant: KIOXIA CORPORATION

Inventor： Naoharu SHIMOMURA ,  Tsuyoshi KONDO ,  Yoshihiro UEDA ,  Yasuaki OOTERA ,  Akihito YAMAMOTO ,  Mutsumi OKAJIMA ,  Masaki KADO ,  Tsutomu NAKANISHI ,  Nobuyuki UMETSU ,  Michael Arnaud QUINSAT

IPC: H01L27/22 ,  H01L43/02

CPC classification number: H01L27/228 ,  H01L43/02

Abstract: A magnetic memory includes first magnetic members extending along a first direction. First and second wirings are spaced apart from the first magnetic members on a second end side of the first magnetic members. At least one of the first magnetic members is between the first and second wirings in a plan view from the first direction. A second magnetic member has a first portion facing the first wiring and electrically connected to a first magnetic member on one side and a second portion facing the first wiring on an opposite side. The second portion is electrically connected to another first magnetic member. A control circuit causes a current to flow through one of the first wiring or the second wiring when data is written into the first magnetic member that is between the first wiring and the second wiring.

公开(公告)号：US20240188307A1

公开(公告)日：2024-06-06

申请号：US18441204

申请日：2024-02-14

Applicant: Kioxia Corporation

Inventor： Masahiro KIYOTOSHI ,  Akihito YAMAMOTO ,  Yoshio OZAWA ,  Fumitaka ARAI ,  Riichiro SHIROTA

IPC: H10B63/00 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/3213 ,  H01L21/762 ,  H01L27/105 ,  H01L29/51 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B69/00 ,  H10B99/00 ,  H10N70/00 ,  H10N70/20

CPC classification number: H10B63/845 ,  H01L21/02532 ,  H01L21/02595 ,  H01L21/30604 ,  H01L21/31055 ,  H01L21/3212 ,  H01L21/32136 ,  H01L21/762 ,  H01L27/105 ,  H01L29/40117 ,  H01L29/513 ,  H01L29/518 ,  H10B43/27 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B63/00 ,  H10B63/20 ,  H10B63/30 ,  H10B69/00 ,  H10B99/00 ,  H10N70/021 ,  H10N70/231 ,  H10N70/801 ,  H10N70/882 ,  H10N70/028 ,  H10N70/20 ,  H10N70/823 ,  H10N70/8413 ,  H10N70/8828 ,  H10N70/8833

Abstract: A semiconductor memory includes a plurality of stripe-like active areas formed by stacking, in a direction perpendicular to a substrate, a plurality of layers extending parallel to the substrate, a first gate electrode formed on first side surfaces of the active areas, the first side surfaces being perpendicular to the substrate, a second gate electrode formed on second side surfaces of the active areas, the second side surfaces being perpendicular to the substrate. The layers are patterned in self-alignment with each other, intersections of the active areas and the first gate electrode form a plurality of memory cells, and the plurality of memory cells in an intersecting plane share the first gate electrode.

公开(公告)号：US20230076828A1

公开(公告)日：2023-03-09

申请号：US17693818

申请日：2022-03-14

Applicant: Kioxia Corporation

Inventor： Naoharu SHIMOMURA ,  Nobuyuki UMETSU ,  Tsuyoshi KONDO ,  Yoshihiro UEDA ,  Yasuaki OOTERA ,  Akihito YAMAMOTO ,  Mutsumi OKAJIMA ,  Masaki KADO ,  Tsutomo NAKANISHI ,  Michael Arnaud QUINSAT

IPC: H01L27/22 ,  H01L43/02 ,  G11C11/16

Abstract: A magnetic memory of the present embodiment includes an electrode extending along a plane including a first direction and a second direction, a first wiring extending in the first direction, second wirings between the electrode and the first wiring, extending in the second direction and arranged in the first direction, first magnetic members each including a first part electrically connected to the first wiring and a second part electrically connected to the electrode, extending in a third direction, and being positioned between neighboring two of the second wirings when seen from the third direction, and a control circuit. When writing first information to one first magnetic member, the control circuit supplies first current to at least two second wirings positioned on one side of the one first magnetic member in the first direction.