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    SEMICONDUCTOR MEMORY
    1.
    发明申请
    SEMICONDUCTOR MEMORY 有权

    公开(公告)号：US20250031378A1

    公开(公告)日：2025-01-23

    申请号：US18908458

    申请日：2024-10-07

    Applicant: Kioxia Corporation

    Inventor： Go OIKE

    IPC: H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L27/06 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/10 ,  H10B43/20 ,  H10B43/27 ,  H10B43/35 ,  H10B43/50 ,  H10B53/20

    Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

    MEMORY BLOCK AND MANUFACTURE METHOD THEREOF
    2.
    发明申请
    MEMORY BLOCK AND MANUFACTURE METHOD THEREOF 有权

    公开(公告)号：US20240414914A1

    公开(公告)日：2024-12-12

    申请号：US18528818

    申请日：2023-12-05

    Applicant: WUHAN XINXIN SEMICONDUCTOR MANUFACTURING CO., LTD.

    Inventor： Kaiwei CAO ,  Wuqian GENG ,  Wei FENG ,  Qiong ZHAN

    IPC: H10B43/23 ,  H10B41/23

    Abstract: The present disclosure provides a memory block and a manufacture method thereof. The memory block includes a substrate, a memory array, and a well-lead-out region. The memory array is arranged on the substrate and includes a plurality of semiconductor-strip-structure columns. The well-lead-out region includes a plurality of well-connection structures. Each semiconductor-strip-structure column extends to the well-lead-out region. In the well-lead-out region, each semiconductor-strip-structure column includes a stepped structure with a plurality of steps. Each well-connection structure corresponds to a corresponding semiconductor-strip-structure column, for electrically connecting channel semiconductor strips in the corresponding semiconductor-strip-structure column together by using the stepped structure in the corresponding semiconductor-strip-structure column.

    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    4.
    发明公开
    SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开

    公开(公告)号：US20240074169A1

    公开(公告)日：2024-02-29

    申请号：US18108953

    申请日：2023-02-13

    Applicant: SK hynix Inc.

    Inventor： In Ku KANG

    IPC: H10B41/23

    CPC classification number: H10B41/23

    Abstract: Provided herein may be a semiconductor device and a method of manufacturing the semiconductor device. The semiconductor device may include a gate stacked structure including a plurality of insulating layers and a plurality of conductive layers that are alternately stacked, a vertical structure extending into the gate stacked structure, a floating gate disposed between the vertical structure and the plurality of conductive layers, and a dielectric pattern disposed between the floating gate and the plurality of conductive layers. The floating gate may include a first portion that is adjacent to the vertical structure and a second portion that is adjacent to the dielectric pattern, and the dielectric pattern may contact an upper surface, a lower surface, and a sidewall of the second portion.

    MEMORY DEVICE AND METHOD OF FORMING THE SAME
    6.
    发明申请
    MEMORY DEVICE AND METHOD OF FORMING THE SAME 有权

    公开(公告)号：US20240381653A1

    公开(公告)日：2024-11-14

    申请号：US18782012

    申请日：2024-07-23

    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.

    Inventor： Chao-I Wu ,  Yu-Ming Lin ,  Sai-Hooi Yeong

    IPC: H10B51/20 ,  H01L21/28 ,  H01L29/51 ,  H10B41/23 ,  H10B51/00 ,  H10B51/10 ,  H10B51/30

    Abstract: Provided are a memory device and a method of forming the same. The memory device includes a substrate, a layer stack, and a plurality of composite pillar structures. The layer stack is disposed on the substrate. The layer stack includes a plurality of conductive layers and a plurality of dielectric layers stacked alternately. The composite pillar structures respectively penetrate through the layer stack. Each composite pillar structure includes a dielectric pillar; a pair of conductive pillars penetrating through the dielectric pillar and electrically isolated from each other through a portion of the dielectric pillar; a channel layer covering both sides of the dielectric pillar and the pair of conductive pillars; a ferroelectric layer disposed between the channel layer and the layer stack; and a buffer layer disposed between the channel layer and the ferroelectric layer.

    SEMICONDUCTOR DEVICE, THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE
    8.
    发明申请
    SEMICONDUCTOR DEVICE, THREE-DIMENSIONAL MEMORY AND FABRICATION METHOD OF SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230134659A1

    公开(公告)日：2023-05-04

    申请号：US18090357

    申请日：2022-12-28

    Applicant: YANGTZE MEMORY TECHNOLOGIES CO., LTD.

    Inventor： Liang Chen

    IPC: H10B41/23 ,  H10B41/10 ,  H10B43/10 ,  H10B43/23

    Abstract: The present disclosure provides a semiconductor device, a three-dimensional memory and a fabrication method of the semiconductor device. The semiconductor device comprises a substrate, a plurality of gates on a first side of the substrate and extending parallelly in a first horizontal direction, a plurality of first contacts each on a corresponding one of the plurality of gates and extending along the first horizontal direction, and a plurality of second contacts on the first side of the substrate, each second contact extends along the first horizontal direction, and is located between adjacent two first contacts and between two corresponding gates.

    Semiconductor memory
    9.
    发明授权
    Semiconductor memory 有权

    公开(公告)号：US12144181B2

    公开(公告)日：2024-11-12

    申请号：US18346473

    申请日：2023-07-03

    Applicant: Kioxia Corporation

    Inventor： Go Oike

    IPC: H10B43/20 ,  H01L23/522 ,  H01L23/528 ,  H01L27/06 ,  H10B41/20 ,  H10B41/23 ,  H10B41/27 ,  H10B41/30 ,  H10B41/70 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35 ,  H10B43/40 ,  H10B43/50 ,  H10B53/20 ,  H01L23/532

    Abstract: A semiconductor memory includes first to fourth stacked bodies. The first stacked body includes a first conductor, and an alternating stack of first insulators and second conductors above the first conductor in a region. The second stacked body includes a third conductor, and an alternating stack of second insulators and fourth conductors above the third conductor in another region. The third stacked body includes a fifth conductor adjacent to the first conductor via a third insulator in a separation region. The fourth stacked body includes a seventh conductor adjacent to the third conductor via a fifth insulator in the separation region. The fifth conductor is electrically insulated from the seventh conductor.

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