公开(公告)号：US20240136229A1

公开(公告)日：2024-04-25

申请号：US18462242

申请日：2023-09-06

Applicant: Applied Materials, Inc.

Inventor： Jody FRONHEISER ,  Sai Hooi YEONG ,  Benjamin COLOMBEAU ,  Balasubramanian PRANATHARTHIHARAN ,  Lequn LIU

IPC: H01L21/8234 ,  H01L21/02 ,  H01L29/15 ,  H01L29/423

CPC classification number: H01L21/823412 ,  H01L21/02507 ,  H01L29/15 ,  H01L29/42392

Abstract: A method of forming a multi-layer semiconductor device on a substrate includes forming a superlattice of a plurality of alternating first layers composed of a first material and second layers formed of a second material, removing the second layers of the superlattice, etching the first material layers to form trimmed first layers therefrom, wherein the quantity of material removed from different ones of the first layers are different amounts, forming a capping layer over the first layers, measuring at least one of the distance between the capping layers formed on the different ones of the first layers, the thicknesses of the different ones of the capping layers formed on different ones of the trimmed first layers, and the different thicknesses of the combined thickness of different ones of the trimmed first layers and the capping layer formed thereover, and based on differences in the measurements, calculating a new thickness of the etched first layers.

公开(公告)号：US20230005844A1

公开(公告)日：2023-01-05

申请号：US17839827

申请日：2022-06-14

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Alexander JANSEN ,  Joung Joo LEE ,  Lequn LIU

IPC: H01L23/532 ,  H01L23/522 ,  H01L21/768 ,  H01L21/67

Abstract: Interconnect structures on a substrate have low resistivity and high dopant interfaces. In some embodiments, the structures may have an opening with a sidewall from an upper surface to an underlying metallic layer of copper, a barrier layer of tantalum nitride formed on the sidewall of the opening, a liner layer of cobalt or ruthenium formed on the barrier layer and on the underlying metallic layer, a first copper layer with a dopant with a first dopant content formed on the liner layer and filling a lower portion of the opening to form a via-the first dopant content is approximately 0.5 percent to approximately 10 percent, and a second copper layer with the dopant with a second dopant content formed on the first copper layer and filling the at least one opening—the second dopant content is more than zero to approximately 0.5 percent of the dopant and is less than the first dopant content.

公开(公告)号：US20230005789A1

公开(公告)日：2023-01-05

申请号：US17839817

申请日：2022-06-14

Applicant: Applied Materials, Inc.

Inventor： Suketu PARIKH ,  Alexander JANSEN ,  Joung Joo LEE ,  Lequn LIU

IPC: H01L21/768 ,  H01L21/02 ,  H01L21/3105 ,  H01L23/532

Abstract: Methods for forming interconnects on a substrate with low resistivity and high dopant interfaces. In some embodiments, a method includes depositing a first copper layer with a dopant with a first dopant content of 0.5 percent to 10 percent in the interconnect by sputtering a first copper-based target at a first temperature of zero degrees Celsius to 200 degrees Celsius, annealing the substrate at a second temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the first copper layer, depositing a second copper layer with the dopant with a second dopant content of zero percent to 0.5 percent by sputtering a second copper-based target at the first temperature of zero degrees Celsius to 200 degrees Celsius, and annealing the substrate at a third temperature of 200 degrees Celsius to 400 degrees Celsius to reflow the second copper layer.