公开(公告)号：US20220005831A1

公开(公告)日：2022-01-06

申请号：US17479789

申请日：2021-09-20

Applicant: Applied Materials, Inc.

Inventor： Jaesoo AHN ,  Thomas KWON ,  Mahendra PAKALA

IPC: H01L27/11597 ,  H01L29/51 ,  H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

Abstract: Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, an opening formed in the film stack, wherein the opening is filled with a channel layer and a center filling layer, and a protective liner layer disposed between the conductive structure and the channel layer.

公开(公告)号：US20210119119A1

公开(公告)日：2021-04-22

申请号：US17112484

申请日：2020-12-04

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01F10/32 ,  H01L43/02 ,  G11C11/16 ,  H01L43/10 ,  H01F41/32 ,  C23C14/06 ,  C23C14/54

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate for MRAM applications. In one embodiment, a magnetic tunnel junction (MTJ) device structure includes a junction structure disposed on a substrate, the junction structure comprising a first ferromagnetic layer and a second ferromagnetic layer sandwiching a tunneling barrier layer, a dielectric capping layer disposed on the junction structure, a metal capping layer disposed on the junction structure, and a top buffer layer disposed on the metal capping layer.

公开(公告)号：US20200259078A1

公开(公告)日：2020-08-13

申请号：US16859350

申请日：2020-04-27

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Xiaodong WANG ,  Mahendra PAKALA ,  Rongjun WANG

IPC: H01L43/12 ,  H01L27/22 ,  G11C11/16

Abstract: Embodiments of the disclosure provide methods for forming MTJ structures from a film stack disposed on a substrate for MRAM applications and associated MTJ devices. The methods described herein include forming the film properties of material layers from the film stack to create a film stack with a sufficiently high perpendicular magnetic anisotropy (PMA). An iron containing oxide capping layer is utilized to generate the desirable PMA. By utilizing an iron containing oxide capping layer, thickness of the capping layer can be more finely controlled and reliance on boron at the interface of the magnetic storage layer and the capping layer is reduced.

公开(公告)号：US20200160884A1

公开(公告)日：2020-05-21

申请号：US16773232

申请日：2020-01-27

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chi Hong CHING ,  Jaesoo AHN ,  Mahendra PAKALA ,  Rongjun WANG

IPC: G11B5/39 ,  H01L21/768 ,  G11C11/15 ,  G11B5/31 ,  G11C11/16

Abstract: Embodiments herein provide film stacks that include a buffer layer; a synthetic ferrimagnet (SyF) coupling layer; and a capping layer, wherein the capping layer comprises one or more layers, and wherein the capping layer, the buffer layer, the SyF coupling layer, or a combination thereof, is not fabricated from Ru.

公开(公告)号：US20180108831A1

公开(公告)日：2018-04-19

申请号：US15712185

申请日：2017-09-22

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Sajjad Amin HASSAN ,  Mahendra PAKALA ,  Jaesoo AHN

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A process sequence is provided to provide an ultra-smooth (0.2 nm or less) bottom electrode surface for depositing magnetic tunnel junctions thereon. In one embodiment, the sequence includes forming a bottom electrode pad through bulk layer deposition followed by patterning and etching. Oxide is then deposited over the formed bottom electrode pads and polished back to expose the bottom electrode pads. A bottom electrode buff layer is then deposited thereover following a pre-clean operation. The bottom electrode buff layer is then exposed to a CMP process to improve surface roughness. An MTJ deposition is then performed over the bottom electrode buff layer.

公开(公告)号：US20170018706A1

公开(公告)日：2017-01-19

申请号：US15199006

申请日：2016-06-30

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Mahendra PAKALA ,  Chi Hong CHING ,  Rongjun WANG

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01F10/14 ,  H01F10/3222 ,  H01L43/08 ,  H01L43/10

Abstract: Embodiments of the disclosure provide methods and apparatus for fabricating magnetic tunnel junction (MTJ) structures on a substrate in for spin-transfer-torque magnetoresistive random access memory (STT-MRAM) applications. In one embodiment, the method includes patterning a film stack having a tunneling barrier layer disposed between a magnetic reference layer and a magnetic storage layer disposed on a substrate to remove a portion of the film stack from the substrate until an upper surface of the substrate is exposed, forming a sidewall passivation layer on sidewalls of the patterned film stack and subsequently performing a thermal annealing process to the film stack.

Abstract translation: 本公开的实施例提供了用于在自旋传递 - 转矩磁阻随机存取存储器（STT-MRAM）应用中在衬底上制造磁性隧道结（MTJ）结构的方法和装置。 在一个实施例中，该方法包括图案化具有设置在磁参考层和设置在基板上的磁存储层之间的隧道势垒层的膜堆叠，以从基板去除一部分膜叠层，直到基板的上表面 暴露，在图案化膜堆叠的侧壁上形成侧壁钝化层，并随后对膜堆叠进行热退火处理。

公开(公告)号：US20240429048A1

公开(公告)日：2024-12-26

申请号：US18745485

申请日：2024-06-17

Applicant: Applied Materials, Inc.

Inventor： Ruiying HAO ,  Thomas KIRSCHENHEITER ,  Arvind KUMAR ,  Mahendra PAKALA ,  Roya BAGHI ,  Balasubramanian PRANATHARTHIHARAN ,  Fredrick FISHBURN

IPC: H01L21/02 ,  H01L29/165

Abstract: A semiconductor device and a method for manufacturing thereof. A substrate is provided. At least one silicon layer is formed on top of the substrate. At least one silicon-germanium layer is formed on top of at least one silicon layer. At least one silicon-germanium layer includes at least one n-type dopant. The semiconductor device having at least one silicon layer and at least one silicon-germanium layer is formed.

公开(公告)号：US20220115439A1

公开(公告)日：2022-04-14

申请号：US17423435

申请日：2020-01-16

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Chando PARK ,  Jaesoo AHN ,  Hsin-wei TSENG ,  Mahendra PAKALA

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/10 ,  H01L43/12

Abstract: Implementations of the present disclosure generally relate to a memory device. More specifically, implementations described herein generally relate to a SOT-MRAM. The SOT-MRAM includes a memory cell having a magnetic storage layer disposed side by side and in contact with a SOT layer. The side by side magnetic storage layer and the SOT layer can achieve the switching of the magnetic storage layer by reversing the direction of the electrical current flowing through the SOT layer without any additional conditions.

公开(公告)号：US20210351342A1

公开(公告)日：2021-11-11

申请号：US16871779

申请日：2020-05-11

Applicant: Applied Materials, Inc.

Inventor： Minrui YUI ,  Wenhui WANG ,  Jaesoo AHN ,  Jong Mun KIM ,  Sahil PATEL ,  Lin XUE ,  Chando PARK ,  Mahendra PAKALA ,  Chentsau Chris YING ,  Huixiong DAI ,  Christopher S. Ngai

IPC: H01L43/08 ,  H01L43/04 ,  H01L43/14 ,  H01L43/10 ,  G11C11/16 ,  H01L27/22 ,  G01R33/09

Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.

公开(公告)号：US20200098981A1

公开(公告)日：2020-03-26

申请号：US16141470

申请日：2018-09-25

Applicant: Applied Materials, Inc.

Inventor： Lin XUE ,  Jaesoo AHN ,  Hsin-wei TSENG ,  Mahendra PAKALA

IPC: H01L43/12 ,  H01L43/10

Abstract: Embodiments of the disclosure relate to methods for fabricating structures used in memory devices. More specifically, embodiments of the disclosure relate to methods for fabricating MTJ structures in memory devices. In one embodiment, the method includes forming a MTJ structure, depositing a encapsulating layer on a top and sides of the MTJ structure, depositing a dielectric material on the encapsulating layer, removing the dielectric material and the encapsulating layer disposed on the top of the MTJ structure by a chemical mechanical planarization (CMP) process to expose the top of the MTJ structure, and depositing a contact layer on the MTJ structure. The method utilizes a CMP process to expose the top of the MTJ structure instead of an etching process, which avoids damaging the MTJ structure and leads to improved electrical contact between the MTJ structure and the contact layer.