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公开(公告)号：US11914299B2
公开(公告)日：2024-02-27
申请号：US17898216
申请日：2022-08-29
IPC分类号： G03F7/20 , H01L21/027 , G03F7/30 , G03F7/38 , G03F7/16
CPC分类号： G03F7/20 , G03F7/16 , G03F7/30 , G03F7/38 , H01L21/0274
摘要： A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US20210294216A1
公开(公告)日：2021-09-23
申请号：US16825393
申请日：2020-03-20
IPC分类号： G03F7/20 , H01L21/027 , G03F7/16 , G03F7/38 , G03F7/30
摘要： A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US20200075409A1
公开(公告)日：2020-03-05
申请号：US16558711
申请日：2019-09-03
发明人： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC分类号： H01L21/768 , H01L21/033 , H01L23/522
摘要： Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.
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公开(公告)号：US20190212656A1
公开(公告)日：2019-07-11
申请号：US16244381
申请日：2019-01-10
发明人： Huixiong Dai , Weimin Zeng , Daniel Lee Diehl , Yong Cao , Hsiang Ning Wu , Khoi Phan , Christopher S. Ngai , Mingwei Zhu , Michael Stolfi , Nelson M. Felix , Ekmini Anuja DeSilva , Xianmin Tang
CPC分类号： G03F7/70058 , G03F7/0035 , G03F7/2022 , G03F7/70033
摘要： Methods for depositing an EUV hardmask film on a substrate by physical vapor deposition which allow for reduced EUV dose. Certain embodiments relate to metal oxide hardmasks which require smaller amounts of EUV energy for processing and allow for higher throughput. A silicon or metal target can be sputtered onto a substrate in the presence of an oxygen and or doping gas containing plasma.
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公开(公告)号：US20180135183A1
公开(公告)日：2018-05-17
申请号：US15806500
申请日：2017-11-08
发明人： Weimin Zeng , Yong Cao , Daniel Lee Diehl , Khoi Phan , Huixiong Dai , Christopher S. Ngai
IPC分类号： C23C16/56 , C23C16/455 , G03F1/22
CPC分类号： C23C16/56 , C23C14/06 , C23C14/5826 , C23C14/5846 , C23C16/0272 , C23C16/455 , G03F1/22
摘要： Processing methods comprising depositing an initial hardmask film on a substrate by physical vapor deposition and exposing the initial hardmask film to a treatment plasma comprising a silane compound to form the hardmask.
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公开(公告)号：US11723283B2
公开(公告)日：2023-08-08
申请号：US16871779
申请日：2020-05-11
发明人： Minrui Yu , Wenhui Wang , Jaesoo Ahn , Jong Mun Kim , Sahil Patel , Lin Xue , Chando Park , Mahendra Pakala , Chentsau Chris Ying , Huixiong Dai , Christopher S. Ngai
CPC分类号： H10N50/10 , G01R33/095 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/85 , H10N52/01 , H10N52/80
摘要： Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
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公开(公告)号：US20220367285A1
公开(公告)日：2022-11-17
申请号：US17875527
申请日：2022-07-28
发明人： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC分类号： H01L21/8234 , H01L29/78 , H01L21/311 , H01L29/40 , H01L29/66
摘要： Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
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公开(公告)号：US11429026B2
公开(公告)日：2022-08-30
申请号：US16825393
申请日：2020-03-20
IPC分类号： G03F7/20 , H01L21/027 , G03F7/16 , G03F7/38 , G03F7/30
摘要： A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US10957590B2
公开(公告)日：2021-03-23
申请号：US16669082
申请日：2019-10-30
发明人： Wenhui Wang , Huixiong Dai , Christopher S. Ngai , Liqi Wu , Wenyu Zhang , Yongmei Chen , Hao Chen , Keith Tatseun Wong , Ke Chang
IPC分类号： H01L21/768 , H01L23/535 , H01L21/02 , H01L21/033 , H01L21/311
摘要： Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.
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公开(公告)号：US20200075422A1
公开(公告)日：2020-03-05
申请号：US16550784
申请日：2019-08-26
发明人： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC分类号： H01L21/8234 , H01L29/78 , H01L29/66 , H01L29/40 , H01L21/311
摘要： Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
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