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公开(公告)号：US11723283B2
公开(公告)日：2023-08-08
申请号：US16871779
申请日：2020-05-11
Applicant: Applied Materials, Inc.
Inventor： Minrui Yu , Wenhui Wang , Jaesoo Ahn , Jong Mun Kim , Sahil Patel , Lin Xue , Chando Park , Mahendra Pakala , Chentsau Chris Ying , Huixiong Dai , Christopher S. Ngai
CPC classification number: H10N50/10 , G01R33/095 , G01R33/098 , G11C11/161 , H10B61/00 , H10N50/85 , H10N52/01 , H10N52/80
Abstract: Embodiments of the present disclosure generally include spin-orbit torque magnetoresistive random-access memory (SOT-MRAM) devices and methods of manufacture thereof. The SOT-MRAM devices described herein include an SOT layer laterally aligned with a magnetic tunnel junction (MTJ) stack and formed over a trench in an interconnect. Thus, the presence of the SOT layer outside the area of the MTJ stack is eliminated, and electric current passes from the interconnect to the SOT layer by SOT-interconnect overlap. The devices and methods described herein reduce the formation of shunting current and enable the MTJ to self-align with the SOT layer in a single etching process.
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公开(公告)号：US20220367285A1
公开(公告)日：2022-11-17
申请号：US17875527
申请日：2022-07-28
Applicant: Applied Materials, Inc.
Inventor： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC: H01L21/8234 , H01L29/78 , H01L21/311 , H01L29/40 , H01L29/66
Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
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公开(公告)号：US11429026B2
公开(公告)日：2022-08-30
申请号：US16825393
申请日：2020-03-20
Applicant: Applied Materials, Inc.
Inventor： Huixiong Dai , Mangesh Ashok Bangar , Srinivas D. Nemani , Christopher S. Ngai , Ellie Y. Yieh
IPC: G03F7/20 , H01L21/027 , G03F7/16 , G03F7/38 , G03F7/30
Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US10957590B2
公开(公告)日：2021-03-23
申请号：US16669082
申请日：2019-10-30
Applicant: Applied Materials, Inc.
Inventor： Wenhui Wang , Huixiong Dai , Christopher S. Ngai , Liqi Wu , Wenyu Zhang , Yongmei Chen , Hao Chen , Keith Tatseun Wong , Ke Chang
IPC: H01L21/768 , H01L23/535 , H01L21/02 , H01L21/033 , H01L21/311
Abstract: Implementations of the present disclosure generally relate to the fabrication of integrated circuits, and more particularly, to methods for forming a layer. The layer may be a mask used in lithography process to pattern and form a trench. The mask is formed over a substrate having at least two distinct materials by a selective deposition process. The edges of the mask are disposed on an intermediate layer formed on at least one of the two distinct materials. The method includes removing the intermediate layer to form a gap between edges of the mask and the substrate and filling the gap with a different material than the mask or with the same material as the mask. By filling the gap with the same or different material as the mask, electrical paths are improved.
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公开(公告)号：US20200075422A1
公开(公告)日：2020-03-05
申请号：US16550784
申请日：2019-08-26
Applicant: Applied Materials, Inc.
Inventor： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC: H01L21/8234 , H01L29/78 , H01L29/66 , H01L29/40 , H01L21/311
Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
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公开(公告)号：US09865464B2
公开(公告)日：2018-01-09
申请号：US15348170
申请日：2016-11-10
Applicant: Applied Materials, Inc.
Inventor： Yongmei Chen , Christopher S. Ngai , Jingjing Liu , Jun Xue , Chentsau Ying , Ludovic Godet
IPC: H01L21/033 , H01L29/49 , H01L27/115 , H01L27/11556 , H01L27/11582 , H01L29/51 , H01L21/02 , H01L21/311 , C23C16/27 , H01L27/11524 , H01L27/1157
CPC classification number: H01L21/0332 , C23C16/26 , C23C16/27 , C23C16/274 , C23C16/279 , H01L21/02115 , H01L21/02274 , H01L21/0335 , H01L21/0337 , H01L21/31111 , H01L21/31122 , H01L21/31144 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L27/11582 , H01L29/49 , H01L29/495 , H01L29/4966 , H01L29/4975 , H01L29/51 , H01L29/518
Abstract: A nanocrystalline diamond layer for use in forming a semiconductor device and methods for using the same are disclosed herein. The device can include a substrate with a processing surface and a supporting surface, a device layer formed on the processing surface and a nanocrystalline diamond layer formed on the processing layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm. The method can include positioning a substrate in a process chamber, depositing a device layer on a processing surface, depositing a nanocrystalline diamond layer on the device layer, the nanocrystalline diamond layer having an average grain size of between 2 nm and 5 nm, patterning and etching the nanocrystalline diamond layer, etching the device layer to form a feature and ashing the nanocrystalline diamond layer from the surface of the device layer.
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公开(公告)号：US12198985B2
公开(公告)日：2025-01-14
申请号：US17875527
申请日：2022-07-28
Applicant: Applied Materials, Inc.
Inventor： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC: H01L29/78 , H01L21/311 , H01L21/8234 , H01L29/40 , H01L29/66
Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts through the selective deposition of a fill material.
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公开(公告)号：US11914299B2
公开(公告)日：2024-02-27
申请号：US17898216
申请日：2022-08-29
Applicant: Applied Materials, Inc.
Inventor： Huixiong Dai , Mangesh Ashok Bangar , Srinivas D. Nemani , Christopher S. Ngai , Ellie Y. Yieh
IPC: G03F7/20 , H01L21/027 , G03F7/30 , G03F7/38 , G03F7/16
CPC classification number: G03F7/20 , G03F7/16 , G03F7/30 , G03F7/38 , H01L21/0274
Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US20210294216A1
公开(公告)日：2021-09-23
申请号：US16825393
申请日：2020-03-20
Applicant: Applied Materials, Inc.
Inventor： Huixiong Dai , Mangesh Ashok Bangar , Srinivas D. Nemani , Christopher S. Ngai , Ellie Y. Yieh
IPC: G03F7/20 , H01L21/027 , G03F7/16 , G03F7/38 , G03F7/30
Abstract: A method for enhancing the depth of focus process window during a lithography process includes applying a photoresist layer comprising a photoacid generator on a material layer disposed on a substrate, exposing a first portion of the photoresist layer unprotected by a photomask to light radiation in a lithographic exposure process, providing a thermal energy to the photoresist layer in a post-exposure baking process, applying an electric field or a magnetic field while performing the post-exposure baking process, and dynamically changing a frequency of the electric field as generated while providing the thermal energy to the photoresist layer.
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公开(公告)号：US20200075409A1
公开(公告)日：2020-03-05
申请号：US16558711
申请日：2019-09-03
Applicant: Applied Materials, Inc.
Inventor： Wenhui Wang , Huixiong Dai , Christopher S. Ngai
IPC: H01L21/768 , H01L21/033 , H01L23/522
Abstract: Methods of forming and processing semiconductor devices which utilize a three-color hardmask process are described. Certain embodiments relate to the formation of self-aligned contacts for metal gate applications. More particularly, certain embodiments relate to the formation of self-aligned gate contacts utilizing selective deposition of masks in a three-color process.
