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公开(公告)号：US20230096309A1
公开(公告)日：2023-03-30
申请号：US17486631
申请日：2021-09-27
发明人： Chang Seok KANG , Tomohiko KITAJIMA , Sung-Kwan KANG , Fredrick FISHBURN , Gill Yong LEE , Nitin K. INGLE
IPC分类号： H01L27/108
摘要： Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.
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公开(公告)号：US20220199627A1
公开(公告)日：2022-06-23
申请号：US17551903
申请日：2021-12-15
发明人： Fredrick FISHBURN , Arvind KUMAR , Sony VARGHESE
IPC分类号： H01L27/108
摘要： Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) devices and replacement channel processes for fabricating 3D DRAM devices. In an example, a gate dielectric layer is formed on a sacrificial material, and a gate electrode is formed on the gate dielectric layer. After the gate electrode is formed, the sacrificial material is removed and replaced by a semiconductor material. A channel region of a device (e.g., a transistor) that includes the gate dielectric layer and gate electrode is formed in the semiconductor material. The channel region can be vertical or horizontal with respect to a main surface of a substrate on which the device is formed. A capacitor can be formed, such as before or after the semiconductor material is formed, and is electrically connected to the semiconductor material. The device and the capacitor together can form at least part of a 3D DRAM cell.
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3.发明公开公开(公告)号：US20230380145A1
公开(公告)日：2023-11-23
申请号：US18141557
申请日：2023-05-01
IPC分类号： H10B12/00 , H10B80/00 , H01L25/065
CPC分类号： H10B12/482 , H10B80/00 , H01L25/0657 , H10B12/488 , H10B12/02
摘要： A semiconductor structure includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including a semiconductor layer, a word line metal layer, and an interface on a cross section of the semiconductor layer, a spacer between adjacent memory levels of the plurality of memory levels in the first direction, and a bit line in contact with the interface of each of the plurality of memory levels, the bit line extending in the first direction. The bit line comprises metal material, and the interface comprises silicide.
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4.发明公开公开(公告)号：US20240347602A1
公开(公告)日：2024-10-17
申请号：US18632003
申请日：2024-04-10
IPC分类号： H01L29/165 , H01L21/02 , H01L21/306 , H01L29/04 , H10B12/00
CPC分类号： H01L29/165 , H01L21/02532 , H01L21/30604 , H01L29/045 , H10B12/00
摘要： A three-dimensional semiconductor (3D) device. The 3D device may include a substrate, and a monocrystalline layer stack. The monocrystalline layer stack may include at least one monocrystalline semiconductor layer, separated from, and disposed over a main surface of the substrate. The 3D device may further include a plurality of epitaxial heterostructures, integrally grown from the at least one monocrystalline semiconductor layer. As such, a first epitaxial heterostructure may be disposed on a lower surface of the at least one monocrystalline semiconductor layer, facing the substrate, and wherein a second epitaxial heterostructure may be disposed on an upper surface of the monocrystalline semiconductor layer, opposite the lower surface.
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公开(公告)号：US20240332023A1
公开(公告)日：2024-10-03
申请号：US18621828
申请日：2024-03-29
发明人： Ying-Bing JIANG , In Seok HWANG , Zhijun CHEN , Avgerinos V. GELATOS , Joung Joo LEE , Xianmin TANG , Fredrick FISHBURN , Le ZHANG , Wangee KIM , Mahendra PAKALA
IPC分类号： H01L21/285 , C23C16/24 , C23C16/34 , C23C16/40 , C23C16/455
CPC分类号： H01L21/28518 , C23C16/24 , C23C16/345 , C23C16/401 , C23C16/45557
摘要： The present disclosure relates to a method of selectively forming a silicide in high-aspect ratio structures by use of a multistep deposition process. A first precursor gas is delivered to a surface disposed within a processing region of a process chamber maintained at a first process pressure, where the substrate is maintained at a first temperature for a first period of time. A purge gas is delivered to for a second period of time after the first period of time has elapsed. A second precursor gas is delivered to the surface of the substrate. The second precursor being maintained at a second process pressure while the substrate is maintained at a second temperature for a third period of time. The purge gas is delivered to the processing region for a fourth period of time after the third period of time has elapsed.
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公开(公告)号：US20220336469A1
公开(公告)日：2022-10-20
申请号：US17688602
申请日：2022-03-07
IPC分类号： H01L27/108
摘要： The present disclosure generally relates to dynamic random access memory (DRAM) devices and to semiconductor fabrication for DRAM devices. Certain embodiments disclosed herein provide an integrated processing system and methods for forming CMOS contact, DRAM array bit line contact (BLC), and storage node structures. The integrated processing system and methods enable deposition of contact and storage node layers with reduced contamination and improved quality, thus reducing leakage current and resistance for the final contact and storage node structures.
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