公开(公告)号：US20240098971A1

公开(公告)日：2024-03-21

申请号：US18236922

申请日：2023-08-22

Applicant: Applied Materials, Inc.

Inventor： Chang Seok KANG ,  Sung-Kwan KANG

IPC: H10B12/00

CPC classification number: H10B12/30 ,  H10B12/03 ,  H10B12/05

Abstract: A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.

公开(公告)号：US20240090213A1

公开(公告)日：2024-03-14

申请号：US18238954

申请日：2023-08-28

Applicant: Applied Materials, Inc.

Inventor： Jialiang WANG ,  Soonil LEE ,  Eswaranand VENKATASUBRAMANIAN ,  Chang Seok KANG ,  Sanjay G. KAMATH ,  Abhijit B. MALLICK ,  Srinivas GUGGILLA ,  Amy CHILD ,  Sung-Kwan KANG ,  Balasubramanian PRANATHARTHIHARAN

IPC: H10B41/35 ,  H01L21/02 ,  H01L21/3065 ,  H01L21/67 ,  H10B43/10

CPC classification number: H10B41/35 ,  H01L21/02164 ,  H01L21/02274 ,  H01L21/3065 ,  H01L21/67063 ,  H10B43/10 ,  H10B80/00

Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.

公开(公告)号：US20240363345A1

公开(公告)日：2024-10-31

申请号：US18441352

申请日：2024-02-14

Applicant: Applied Materials, Inc.

Inventor： Chang Seok KANG ,  Raman GAIRE ,  Hsueh Chung CHEN ,  In Soo JUNG ,  Houssam LAZKANI ,  Balasubramanian PRANATHARTHIHARAN

IPC: H01L21/02 ,  H01L21/20 ,  H01L21/306

CPC classification number: H01L21/02645 ,  H01L21/02532 ,  H01L21/2003 ,  H01L21/306

Abstract: A method for manufacturing a memory device includes depositing a seed layer in a memory hole extending through a memory stack. The seed layer includes particles, such as silicon particles. The seed layer is etched to produce etched particles. The etched particles act as nuclei for the growth of a crystalline channel material in the memory hole.

公开(公告)号：US20230096309A1

公开(公告)日：2023-03-30

申请号：US17486631

申请日：2021-09-27

Applicant: Applied Materials, Inc.

Inventor： Chang Seok KANG ,  Tomohiko KITAJIMA ,  Sung-Kwan KANG ,  Fredrick FISHBURN ,  Gill Yong LEE ,  Nitin K. INGLE

IPC: H01L27/108

Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.

公开(公告)号：US20220285362A1

公开(公告)日：2022-09-08

申请号：US17674353

申请日：2022-02-17

Applicant: Applied Materials, Inc.

Inventor： Fredrick David FISHBURN ,  Arvind KUMAR ,  Sony VARGHESE ,  Chang Seok KANG ,  Sung-Kwan KANG ,  Tomohiko KITAJIMA

IPC: H01L27/108 ,  G11C5/10

Abstract: Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.